SONET/SDH OC-3 Transceiver/CDR

The SMS2011 SONET/SDH is a fully integrated Clock Data Recovery (CDR) SONET OC-3 interface core designed for multiple integration on a single IC in a typical System-On-Chip (SOC) application. SMS2011 interfacing to the rest of building blocks on chip is fully customizable. For example, an optional mux demux module can be interconnected to the SMS2011 core making it capable of performing all the necessary serial-to-parallel and parallel to-serial functions in compliance with SONET/SDH transmission standards. The SMS2011 block diagram is shown in Figure 1. In a typical SOC application, 16 instances of SMS2011, 4 instances of SMS2012 (SONET/SDH OC-12 CDR/TRANSCEIVER) and an additional 2 million of logic gates can be integrated on a single chip.

SMS2011 CDR block contains a clock recovery unit with an integrated loop filter allowing the use of a slower clock reference. SMS2011 performs the clock recovery task by utilizing proprietary Advanced Signal Processing techniques. The interface to an external optical module could be either LVPECL or LVDS. The low jitter LVPECL/ LVDS interface guarantees compliance with the bit-error rate requirements of the ITU standards.

• Innovative (patent pending) CMOS architecture to guarantee compliance with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer, and jitter generation
  Designed for multiple integration in typical SOC applications
  High frequency PLLs with integrated on chip loop filters
  Advanced Signal Processing techniques utilized for clock recovery
  Supports 155.52 Mbit/s (OC-3)
  Selectable reference frequencies of 19.44, 77.76 or 155.52 MHz
  LVPECL or LVDS logic for external interfacing to optical units
  Diagnostic Loopback mode

• SONET/SDH-based transmission systems
• WDM/ DWDM aggregator ICs
• SONET/SDH modules
• SONET/SDH test equipment
• Packet Over SONET (POS)
• ATM over SONET
• IP over SONET
• Add Drop Multiplexer (ADM)
• Broad-band cross-connects

• GDS II stream file.
• Application Documentation.