Vendor: Pacific MicroCHIP Corp. Category: Filters Transforms

Cross-Correlator Matrix 64x64

PMCC_XCM_64x64_D IP block is a low-power array of 1GHz clocked Cross-Correlator cells that are synchronously acquiring two sets o…

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Overview

PMCC_XCM_64x64_D IP block is a low-power array of 1GHz clocked Cross-Correlator cells that are synchronously acquiring two sets of 64x2-bit data streams which are derived by digitizing IF signals at a 2-bit precision. The IP block is cross-correlating and preparing the data for further processing.
The PMCC_XCM_64x64_D IP block consists of 4096 cross-correlation cells, 64 vertical totalizers, 64 horizontal totalizers, an output multiplexer, a control circuit and the I2C slave controller with registers.
The input data {-3, -1, 1, 3} from two arms is supplied to the cross-correlation cell (XCC) which includes a multiplication unit implemented as a look-up table (LUT). There are five possible result values {0, 2, 3, 4, 6}. Therefore, each LUT has 4 binary inputs and a 3-bit correlation result. The outputs of LUTs are used as input data for counters, which count each input number. To ensure 10ms integration time, 26-bit counters are required. Power efficient ripple counters are employed for this purpose. The result of the cross-correlation is stored in the counters ready to be transmitted through common bus on demand.
The purpose of totalizers (TOTs) is to count the number of occurrences of each possible two-bit input value {-3, -1, 1, 3}. There are 64 vertical (TOTV) and 64 horizontal (TOTH) totalizers. A separate TOT is employed for each input channel. The TOT consists of a multiplication unit (LUT) and four 26-bit synchronous counters.
During the readout mode correlated data comes by the line to the multiplexer (MUX) with serialized 8 bit output. Optionally, an external clock can be applied to control the reading data rate.

Key features

  • Computed correlation of a pair of two-bit inputs, “a” and “b” {-3, -1, 1, 3}
  • 64x64 correlation cells matrix.
  • 1 GHz clock signal.
  • I2C programming interface up to 1MHz.
  • Serialized 8 bit output data.
  • Additional clock input for matrix readout.
  • Implemented 10ms on-chip integration time.
  • Programmable integration and reading time.
  • Totalizer counts the number of occurrences of each possible 2-bit input values {-3, -1, 1, 3}.
  • Totalizer input data rate is 2Gb/s.
  • Power per correlation cell is <0.37mW.
  • Implemented design for testability features (BIST).
  • Input registers to store Read/Write test data.
  • Minimized power consumption.
    • Tristate output buffer.
    • HSTL compatible I/Os.
    • HSTL buffers with adjustable termination resistor to accommodate variety of applications.
    • Radiation hardened (TID and SEL immune) process.

Block Diagram

PMCC_XCM_64x64_D block diagram

Benefits

  • PMCC_XCM_64x64_D IP block is a low-power array of 1GHz clocked Cross-Correlator cells that are synchronously acquiring two sets of 64x2-bit data streams which are derived by digitizing IF signals at a 2-bit precision. The IP block is cross-correlating and preparing the data for further processing.

Applications

  • Radio astronomy
  • Synthetic aperture radar
  • Cross-correlation systems
  • Image processing
  • Complex meteo analyzers
  • Interferometry
  • Synthetic imaging
  • Digital phase detectors
  • • Digital signal processing

What’s Included?

  • GDSII file
  • Netlist for Spectre simulation
  • Layout and Schematic (DRC & LVS) verification reports
  • Datasheet
  • Optional deliverables are:
    • Library containing entire hierarchy of the IP block’s schematic and layout cells
    • Extracted views containing parasitic components from layout
    • Verilog model replicating the IP block’s functionally
    • Simulation test-benches

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
PMCC_XCM_64x64_D
Vendor
Pacific MicroCHIP Corp.
Type
Silicon IP

Provider

Pacific MicroCHIP Corp.
HQ: USA
Pacific MicroCHIP Corp. is a privately held ASIC design company headquartered in Culver City, California, USA. We provide ASIC products, design services and IP blocks for a wide range of ASICs used in precision instrumentation, fiber optic and wireless communications, DNA storage as well as for variety of other applications.
Contact Pacific MicroCHIP Corp.

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What is Cross-Correlator Matrix 64x64?

Cross-Correlator Matrix 64x64 is a Filters Transforms IP core from Pacific MicroCHIP Corp. listed on Semi IP Hub.

How should engineers evaluate this Filters Transforms?

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