Vendor: RFIC Solutions, Inc. Category: Clock Generator

CMOS Low Power Programmable Frequency Divider(50-2400 MHz)

Key features

  • 1. 5 to 10 Bit dividing facility.
  • 2. Ease of customization and fast deliverable IP as
  • per customers need
  • 3. Decoder for selecting same input and output.
  • 4. Available in both categories i.e. GDS II for ASIC and programmable bit stream for FPGA’s as deliverables.

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
RPDA12
Vendor
RFIC Solutions, Inc.
Type
Silicon IP

Provider

RFIC Solutions, Inc.
HQ: United States
RFIC Solutions, Inc. is a fabless semiconductor company focused exclusively on wireless Solutions. RFIC Solutions Inc. offer RFIC, Analog, Digital & Mixed signal IC design services. RF Modules/Board design Services & FPGA design & development services are also provided. RFIC Solutions designs highly integrated system on chip (SOC) and system on a package (SOP); custom ICs, MIC for any wireless systems including cellular, Wi-Fi, WLAN, WiMax and UWB systems. We have designed more than 600 RFICs covering frequency range from 0.01 to 100 GHz. We have expertise in designing LNA, PA, VCO, PLL, complete Transceiver IC, ADC, Mixers, SPDT/DPDT switches at high frequency, 6Bit Attenuator, Complex Band Pass Filter, Op-Amp, PGA, VGA, Prescaler for applications ranging from DC to 40 GHz. These designs are available on SiGe BiCMOS, Si CMOS InGaP, RFCMOS, GaAs pHEMT, technologies provided by our foundry partners Tower Jazz semiconductor, GCS, TSMC, Triquint, Globalfoundries, IBM, Win semiconductors.

Learn more about Clock Generator IP core

Generating multiple clock frequencies using Specman "real" feature in mixed (Analog/Digital) design environments

Using our “Specman agent approach for the Mixed Verification” along with exploiting “real” feature of Specman version 8.2, we can introduce directed/constrained randomization to the frequencies needed for the analog modules which are interacting with the DUT (Design Under Test). This approach gives complete controllability over the clock frequencies, which can be directly randomized and modified on-the-fly from the testcase, as the scenario may demand.

M31 on the Specification and Development of MIPI Physical Layer

MIPI is the abbreviation of "Mobile Industry Processor Interface". This article will introduce the physical layer specifications of MIPI architecture, and explain the features and benefits of D-PHY and C-PHY respectively. Then, the MIPI perspective on the development and challenges of automotive electronics and the professional MIPI technical services that M31 can provide will be shared.

Silicon-Accurate Fractional-N PLL Design

Fractional-N PLLs are a useful class of PLLs and not well understood. This paper explains in simple terms how these differ from a regular integer PLL. Common applications are listed along with a brief description of the key performance parameter – jitter.

FPGA Implementation of DLX Microprocessor With WISHBONE SoC Bus

DLX is an open source microprocessor, it’s free and it has never been implemented in a commercial ASIC (Application Specific Integrated Circuit) design. The objective of this project is to use the DLX microprocessor implemented with Wishbone bus interface for a SoC (System-on-Chip) design.

Mixed Signal Drivers for Ultra Low Power and Very High Power Applications

Evolving niche markets, such as ICs for biomedical applications, are very challenging in respect to power consumption and on chip power dissipation, namely, wide range from ultra low power (ULP) functionality (<uW) where IC is battery powered, e.g. mobile micro transducers, to very high power (VHP, >5W), e.g. coded energy transfer from RFID¡¯s for remote sensing and animal tracking.

Frequently asked questions about Clock Generator IP cores

What is CMOS Low Power Programmable Frequency Divider(50-2400 MHz)?

CMOS Low Power Programmable Frequency Divider(50-2400 MHz) is a Clock Generator IP core from RFIC Solutions, Inc. listed on Semi IP Hub.

How should engineers evaluate this Clock Generator?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Clock Generator IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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