Vendor: SmartDV Technologies Category: Test / Debug

CJTAG (IEEE 1149.7) Verification IP

CJTAG (IEEE 1149.7) Verification IP provides an smart way to verify the CJTAG (IEEE 1149.7) component of a SOC or a ASIC.

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Overview

CJTAG (IEEE 1149.7) Verification IP provides an smart way to verify the CJTAG (IEEE 1149.7) component of a SOC or a ASIC. The SmartDV's CJTAG (IEEE 1149.7) Verification IP is fully compliant with standard CJTAG (IEEE 1149.7) Standard and provides the following features.

CJTAG (IEEE 1149.7) Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

CJTAG (IEEE 1149.7) Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Fully compatible with IEEE 1149.7 standard.
  • Can be used as TAP controller (slave) or TAP instruction/data generator (Master) for CJTAG.
  • Comes with CJTAG monitor to check and report any protocol violation.
  • Supports TAP.7 capability classes T0 to T5
  • Supports Extended Protocol Unit (EPU) for classes 0 to 3
  • Supports all mandatory and optional EPU commands
  • Supports Advanced Protocol Unit (APU) for classes 4 and 5
  • Supports 4 and 2 pin interface as specified in CJTAG (IEEE 1149.7)
  • Supports all mandatory and optional scan formats (JScan, MScan, OScan, and SScan)
  • CJTAG (IEEE 1149.7) supports following scan terminology
    • Data Register Scan
    • Instruction Register Scan
    • Control Register Scan
    • Zero-Bit Scan
  • Can be extended with user defines instructions and registers.
  • Supports optional reset signal.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Callbacks support for BFM and Monitor.
  • Status counters for various events on bus.
  • CJTAG Verification IP comes with complete test suite to test every feature of CJTAG (IEEE 1149.7) specification.

Block Diagram

CJTAG (IEEE 1149.7) VIP block diagram

Benefits

  • Faster testbench development and more complete verification of CJTAG (IEEE 1149.7) designs.
  • Easy to use command interface simplifies testbench control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the CJTAG (IEEE 1149.7) testcases.
  • Examples showing how to connect various components and usage of BFM and Monitor.
  • Detailed documentation of all classes, tasks and functions used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
CJTAG (IEEE 1149.7) VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about SerDes Test / Debug IP cores

What is CJTAG (IEEE 1149.7) Verification IP?

CJTAG (IEEE 1149.7) Verification IP is a Test / Debug IP core from SmartDV Technologies listed on Semi IP Hub.

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Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

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