Overview
The GRSHYLOC IP enables lossless compression for multi-spectral and hyper-spectral images according to the CCSDS121 and CCSDS123 standards.
The IP features a DMA engine to fetch the raw image and store the compressed bitstream from/to external memory through the AMBA AHB master interface.
GRSHYLOC implements a wrapper for the SHYLOC compressor, enabling two possible configurations by means of a generic. Both configurations have common control and data interfaces. The compressed samples are temporary stored into a local SRAM. This reduces the risk of missing output data in case of delays accessing the AHB bus. The content of the memory is written to the external memory when the DMA controller is not busy fetching raw data for the SHYLOC core. GRSHYLOC also includes an AMBA AHB slave interface for configuration and control. There are three sets of registers: one for configuring the CCSDS123 IP, another for the CCSDS121 encoder (optional) and a global set for controlling the overall compression process.
The block diagrams show the two possible configurations for GRSHYLOC. The first one involves the complete SHYLOC system: the CCSDS123 IP performs the prediction stage, whereas CCSDS121 implements the block-adaptive coding. On the other hand, the second configuration only instantiates the CCSDS123, which performs both as predictor and as sample-adaptive encoder.
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