Vendor: ZeroPoint Technologies AB Category: Data Compression

On-chip memory expansion

The Cache MX IP compresses on-chip L2, L3 SRAM cache enabling 2x effective capacity.

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Overview

The Cache MX IP compresses on-chip L2, L3 SRAM cache enabling 2x effective capacity. SRAM Caches can take upto 30-50% of an SoC xPU silicon real estate and a significant power budget that increases with physical dimensions. While digital logic scales effectively with process technology node shrink, SRAM essentially stopped scaling from 5nm to 3nm technology nodes. The number of compute cores demands higher SRAM capacity to effectively scale compute IPC performance. Increasing SRAM area can negatively impact both the die cost as well as die yield. Cache MX offers a power, area and cost effective alternative to enable performance scaling with single digit latency.

The Cache MX IP compresses on-chip L2, L3 SRAM cache enabling 2x effective capacity. SRAM Caches can take upto 30-50% of an SoC xPU silicon real estate and a significant power budget that increases with physical dimensions. While digital logic scales effectively with process technology node shrink, SRAM essentially stopped scaling from 5nm to 3nm technology nodes. The number of compute cores demands higher SRAM capacity to effectively scale compute IPC performance. Increasing SRAM area can negatively impact both the die cost as well as die yield. Cache MX offers a power, area and cost effective alternative to enable performance scaling with single digit latency.

Key features

  • On-the-fly compression / decompression of cache lines
  • Optional secureTraining on metadata capability
  • Silicon Verified TSMC N5
  • On-the-fly Multi-algorithm switching capability without recompression

Benefits

  • Standards
    • Z-Trainless (proprietary)
    • Z-ZID (proprietary)
  • Architecture
    • Modular architecture, enables seamless scalability: Multiple, independent Cache MX instances can coexist within SoC without requiring co-ordination
    • Architectural configuration parameters accessible to fine tune performance

Applications

  • Server CPUs, Smart devices and Embedded systems all face the same challenge. The memory bandwidth is limiting the system scaling and the many cores and accelerators are fighting to serve their memory access requests. A wide range of data set from these different applications have been evaluated and they all verify that it is evident that bandwidth acceleration provides a very efficient and effective way to utilize the full memory potential.

What’s Included?

  • Performance evaluation license C++ compression model for integration in customer performance simulation model
  • HDL Source Licenses
    • Synthesizable System Verilog RTL (encrypted)
    • Implementation constraints
    • UVM testbench (self-checking)
    • Vectors for testbench and expected results
  • User Documentation
  • FPGA evaluation license
    • Encrypted IP delivery (Xilinx)

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Cache MX
Vendor
ZeroPoint Technologies AB

Provider

ZeroPoint Technologies AB
HQ: Sweden
ZeroPoint Technologies is a fabless silicon IP (intellectual property) provider of real-time main memory compression and encryption technology. ZeroPoint Technologies is offering a patented memory compression technology for high performance System on a Chip (SoC) processor subsystems. The technology effectively doubles the main memory capacity and memory bandwidth. Our IP-block is placed on the main memory access path and is transparent to the operating system and applications. ZeroPoint also offers main memory encryption, a technology that delivers high throughput and high security memory encryption, integrated with compression or stand alone. ZeroPoint Technologies AB was incorporated in 2015 as a spinout from Chalmers University of Technology. The Intellectual Property Portfolio related to computer memory management was then acquired from the founders and transferred into the new startup. The technology and ideas behind ZeroPoint come from Professor Per Stenström’s research group, which is internationally recognized for research excellence within high-performance computing. Since its creation, ZeroPoint has attracted skilled people from academia, industry, finance and the startup community and raised its first round of Venture Capital in 2016. The headquarter is in Göteborg, Sweden.
Contact ZeroPoint Technologies AB

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Frequently asked questions about Data Compression IP

What is On-chip memory expansion?

On-chip memory expansion is a Data Compression IP core from ZeroPoint Technologies AB listed on Semi IP Hub.

How should engineers evaluate this Data Compression?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Data Compression IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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