Vendor: Cadence Design Systems, Inc. Category: DSP Core

Cache-Coherent HiFi 5s Symmetric Multiprocessor

Efficient 32-bit processing for audio enhancement algorithms, wideband voice codecs, and multi-channel audio The Cadence® Tensili…

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Overview

Complex Audio and AI Processing Combined with Ease of Programming

Most audio and speech system on chips (SoCs) utilize multiple Cadence Tensilica HiFi DSPs to manage complex codecs and advanced processing, often combining traditional DSP and AI algorithms. Typically, these DSPs are deployed in a non-coherent manner, requiring manual partitioning of algorithms and synchronization, which can lead to challenges like resource fragmentation and software reliability issues. The first issue results in underutilization of compute resources, leading to product feature/quality tradeoffs. The second increases system validation time with a high likelihood of costly errors escaping to the field.

The Cadence Tensilica Cache-Coherent HiFi 5s Symmetric Multiprocessor (SMP) unburdens the software from the treacherous task of inter-processor synchronization. Manual resource partitioning for compute cores and memory is avoided. Software can now focus on dynamic sharing of all available resources, thereby unlocking rich, context-sensitive adaptive features. With hard partitioning eliminated, microphone input and speaker output data paths can all be sent to the same subsystem. Input and output software algorithms, whether from internal teams or external partners, can easily share common resources to achieve optimal performance.

With all the limitations of non-coherent architecture avoided, software reliability and time to market are greatly improved, decreasing development costs and enhancing customers’ competitiveness.

Feature

Cache-Coherent HiFi 5s SMP

Number of Cores

2 to 8

L2 Size

Up to 8MB

L2 Config

All RAM, all cache or hybrid

L2 Clock Rate

Same as HiFi 5s core frequency

L2 Performance Features

Up to 64 outstanding transactions

L2 Bandwidth

64GB or 128GB R/W at 1GHz

Coherency Protocol: Core L1$ to L2$/L2RAM

ACE

Coherency Protocol: Core L2$/L2RAM to L3

ACE-Lite

Coherency Protocol: Host to L2$/L2RAM

ACE-Lite with ACP (Accelerator Coherency Port) support

HiFi 5s iDMA Protocol to L3

ACE-Lite

Host to HiFi 5s DTCM Protocol

AXI4
Multiprocessor Debug APB/ATB/JTAG
Interrupt Distributer Broadcast, dedicated, and interprocessor

Key features

  • Scalable SMP built on the highest performing audio DSP, the HiFi 5s DSP
  • Hardware-managed coherency
  • Multicore RTOS eases application programming
  • Fully supported by XTSC SystemC simulation

Block Diagram

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Benefits

Hardware-Snooped Cache Coherency

Eliminates the need for software-based coherency, as coherency between cores is handled in hardware through L1$ snooping and L2$ management

Scalable SMP Performance

Supports symmetric multiprocessing with two to eight identical HiFi 5s DSPs, ensuring scalable performance. Supports limited synchronization with host based on Arm ACP protocol

Multicore Realtime OS

Supports multiple real-time operating systems, including Multicore Zephyr, Multicore FreeRTOS, and Multicore XOS, providing flexibility and reliability.

Cluster Control

Includes features such as an interrupt distributor, APB, JTAG, TRAX, and power shutoff, ensuring efficient cluster control and management

Applications

  • Automotive,
  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace,
  • Others

Specifications

Identity

Part Number
Cache-Coherent HiFi 5s SMP
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
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Frequently asked questions about DSP Core IP cores

What is Cache-Coherent HiFi 5s Symmetric Multiprocessor?

Cache-Coherent HiFi 5s Symmetric Multiprocessor is a DSP Core IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this DSP Core?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DSP Core IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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