Vendor: Synopsys, Inc. Category: DSP Core

ARC VPX DSPs are VLIW/SIMD processors optimized for highly parallel processing with minimal energy and area consumption for a range of embedded workloads

The Synopsys ARC® VPX DSP Family is optimized for the unique power, performance and area (PPA) requirements of embedded workloads…

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Overview

The Synopsys ARC® VPX DSP Family is optimized for the unique power, performance and area (PPA) requirements of embedded workloads such as IoT sensor fusion, radar and LiDAR processing, engine control, voice/speech recognition, natural language processing and other edge AI applications. The VPX processors are based on an enhanced ARCv2DSP instruction set and operate on 128-bit (VPX2, VPX2FS) and 256-bit (VPX3, VPX3FS) vector words, complementing the existing 512-bit VPX5 and VPX5FS based on the same very long instruction word (VLIW)/single instruction-multiple data (SIMD) architecture.

The safety-enhanced ARC VPXxFS processors integrate hardware safety features including error correction code (ECC) protection for memories and interfaces, safety monitors and lockstep mechanisms that help designers achieve the most stringent levels of ISO 26262 ASIL B, ASIL C and ASIL D functional safety compliance.

The VPX processors are supported by the Synopsys ARC MetaWare Development tools, including a vector length-agnostic software programming model specifically optimized for the VPX hardware architecture. The MetaWare compiler’s auto-vectorization feature transforms sequential code into vector operations for maximum throughput.

Key features

  • ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
  • ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
  • Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

Benefits

  • ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed.
  • The ARChitect wizard enables drag-and-drop configuration of the core, including options for Instruction, program counter and loop counter widths
  • Register file sizeTimers, reset and interrupts Byte ordering Memory type, size, partitioning, base address Power management, clock gating Ports and bus protocol Multipliers, dividers and other hardware features Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT).
  • Adding/removing instructions

Files

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Specifications

Identity

Part Number
dwc_arc_vpx_dsp_processors
Vendor
Synopsys, Inc.
Type
Silicon IP

Provider

Synopsys, Inc.
HQ: USA
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
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Frequently asked questions about DSP Core IP cores

What is ARC VPX DSPs are VLIW/SIMD processors optimized for highly parallel processing with minimal energy and area consumption for a range of embedded workloads?

ARC VPX DSPs are VLIW/SIMD processors optimized for highly parallel processing with minimal energy and area consumption for a range of embedded workloads is a DSP Core IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this DSP Core?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DSP Core IP.

Can this semiconductor IP be compared with similar products?

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