Vendor: Institute of Electronics and Computer Science Category: DMA

AXI4 Memory-Mapped to/from AXI4-Stream DMA

The AXI4-DMA IP core interfaces AXI4 data bus to provide data transfers from AXI4 Memory-Mapped port to AXI4-Stream port or the o…

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Overview

The AXI4-DMA IP core interfaces AXI4 data bus to provide data transfers from AXI4 Memory-Mapped port to AXI4-Stream port or the other way round thus serving as a Direct Memory Access controller.

The core is supplied as independent Memory-Mapped to Stream and Stream to Memory-Mapped single DMA channel modules each with its own AXI4-LITE slave. The modules operate in direct register mode, where control and status registers (CSR) are used to configure descriptors and trigger transfers from the host system. Data bus width, address width, burst length and other parameters are customizable at synthesis time, allowing flexible resource management and adjusment for diverse peripherals. Stream master and slave logic includes convenient data width converters supporting byte alligned 8, 16, 24, 32 and higher bit widths.

The EDI-AXI4-DMA core is provided as VHDL source or packaged for the Xilinx IP Integrator tool and can be combined with other Xilinx IP cores. The parameters are completely configurable in the package allowing the designer to adjust for different peripherals.

Key features

  • AXI4 Memory-Mapped to AXI4-Stream/AXI4 Memory-Mapped to AXI4-Stream DMA
    • Independent AXI4 compliant single channel modules
    • AXI4-Lite port for access to control and status registers
    • Descriptors configured and transfers triggered from control registers in Direct Register Mode
    • End of transfers reported in status register
    • Packaged for Xilinx Vivado® IP Integrator
  • Synthesis Configuration Parameters
    • Data bus width (32 to 1024 bits)
    • Address bus (32 or 64 bits)
    • Maximum burst size (up to 256)
    • FIFO size
    • TLAST triggered interrupt
    • Stream width 8, 16, 24, 32 bits and higher

Block Diagram

EDI-AXI4-DMA block diagram

Applications

  • The core is suitable for AXI4 interconnected systems with AXI4-Stream compatible peripherals, that require software triggered data transfers from shared memory. Data width converter with 24 and 48 bit capabilities is convenient for video processing data formats.

What’s Included?

  • The deliverable includes the packaged core, a testbench with multiple test cases, a simulation and a thorough datasheet. The driver software is available freely under GPL license.

Specifications

Identity

Part Number
EDI-AXI4-DMA
Vendor
Institute of Electronics and Computer Science
Type
Silicon IP

Provider

Institute of Electronics and Computer Science
HQ: Latvia
EDI is the highest-ranking Latvian scientific institute in the field of engineering and technologies. EDI specializes in the development of smart embedded cooperative systems with the sole purpose of creating knowledge and innovative technologies for new products with high added value. EDI has an impressive record of participation in international European framework projects and collaboration with the world's leading companies. Within these collaborations, EDI leverages European ICs and integrates them into novel applications, e.g. fail-operational autonomous driving, AI-based perception, collaborative robotics, wearable electronics, UAVs and others. EDI researchers excel in application-oriented research and have an extensive record of designing digital circuits for the industry, including implementations of stereo-vision accelerators, infra-red image processing algorithms, state-of-the-art spatial image transformation for lens distortion correction and image registration, regex accelerator for hardware-based firewall, optical flow for SLAM algorithm acceleration among others. Currently, EDI packs developed accelerator streams into ICs for use by the industry in demanding computer vision products (https://www.edi.lv/en/projects/silicon-ip-design-house-silhouse-part-2/). EDI also has experience in analogue chip design and uses the taped-out chips to reduce the size of EDI UWB RADAR (https://www.edi.lv/en/solutions/uwb-impulse-radar-kit/). Furthermore, EDI embodies the national expertise in Heterogeneous System on Chip (HSoC) technology that leverages both - software and digital design paradigms for efficient and high-performance next-generation use-cases.
Contact Institute of Electronics and Computer Science

Learn more about DMA IP core

DMA IP Integration

There are many IP’s today . These IP’s can be simple IP’s like Timer to complex IP’s like Accelerators. In Most of the cases IP’s are Integrated in standard way. There are cases where you have the option of Integrating it differently. This goes un-noticed or unable to be implemented due to time constraints. One such IP that would be discussed in this paper is DMA . This paper tries to explain idea of Integrating Direct Memory access(DMA) and Interrupt Control Unit(ICU) differently but final implementation requires some changes in IP. There is a possibility that alternate design explained below may be already implemented.

Frequently asked questions about DMA IP

What is AXI4 Memory-Mapped to/from AXI4-Stream DMA?

AXI4 Memory-Mapped to/from AXI4-Stream DMA is a DMA IP core from Institute of Electronics and Computer Science listed on Semi IP Hub.

How should engineers evaluate this DMA?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DMA IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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