DMA Unit

Up to 64 byte data transfer in CAN FD frames

The DMU signals to the attached DMA Controller (DMA request) when there is a newly received message available at one of the attached M_CAN's Rx FIFOs respectively when there is the possibility to load a new Tx message into the M_CAN's Tx FIFO/Queue.

The DMA controller then autonomously transfers the received message from the M_CAN's Message RAM to the System Memory or the message to be transmitted from the System Memory to the M_CAN's Message RAM.

After the DMA transfer has completed, the DMU acknowledges this to the M_CAN's Rx FIFO respectively sets the related M_CAN's transmission request.

• Enables real-time control loops
• Deterministic multi-threaded architecture (8 threads per RISC unit)
• Programmability (special purpose RISC/ALU)
• Scalable and configurable architecture
• Easy integration due to generic interfaces and hierarchical architecture
• SystemC model support for in-system verification and early software development
• Supports model-based development
• 5 ns input and output resolution for high-precision data capturing and data signal generation

• Offloads tasks from the CPU to the DMA controller
• Enables DMA transfers of M_CAN FIFO elements and optional TSU timestamps between Message RAM and system memory.
• Available for integration into microcontrollers, ASICs, and FPGAs.

• VHDL source code,
• test environment (test bench and integration tests),
• SystemC executable model for in-system verification and early software development,
• documentation,
• application notes,
• serial communication protocol software drivers