Vendor:
Certus Semiconductor
Category:
ESD Protection
5V ESD Clamp in GlobalFoundries 180nm LPe
A GlobalFoundries 180nm LPe Specialized 5V ESD Clamp.
Overview
A GlobalFoundries 180nm LPe Specialized 5V ESD Clamp.
A key attribute of this 5V Clamp is that it can be used for either signal protection or 1.8V power supplies. The clamp is a single cell, 44um x 32um in size. It is built from the substrate to metal 6. The clamp is very dense in metal, and diffusion, a wide area around the clamp (3um to 10um) should have minimum metals between layers 1 and 3, as well as little diffusion, to pass directly to chip top.
Cell Names and Variation
| Cell Name | Description |
| ESD50_ggnmos | Standard 5V Clamp |
Pin Out and Function
| Parameter | Description |
| PAD50 | Signal/Power |
| VSS | Ground |
| SUB | SOI-Substrate |
Electrical Specifications
| Parameter | Description | Min | Typical | Max | Unit |
| Vm ax | Max Voltage at PAD 50 | -0.5 | 5 | 5.6 | Volts |
| Il eak | Leakage Current | N/A | 1.5 | 15 | nA |
| Cm ax | Load Capacitance | N/A | N/A | 0.5 | pF |
Metallization
- PAD50 (Metal 4): Primary ESD current path. Robust connection, in wide thick metals and losts of vias, compliant with ESD.
- VSS (Metal 4): Primary ESD current path. Robust connection, in wide thick metals and losts of vias, compliant with ESD
- SUB (schematic only): There is no layout connection for SUB. This is the SUB connection inherent to whatever layout top level the clamp is placed into. The CDL netlit, however, has pin for it, and must connect to the SUB net of the top-level block the layout is placed in GROUND reference for ESD.
Block Diagram
5V ESD Clamp in GlobalFoundries 180nm LPe block diagram
Files
Note: some files may require an NDA depending on provider policy.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 180nm | 180 1800 nm | — |
Specifications
Identity
Part Number
5V ESD Clamp in GlobalFoundries 180nm LPe
Vendor
Certus Semiconductor
Provider
Certus Semiconductor
HQ:
United States
Certus Semiconductor has assembled several of the world’s foremost experts in IO and ESD design to offer our clients the ability to affordably tailor their IO libraries into the optimal fit for their products. Certus is offering the semiconductor industry a unique approach to custom IO libraries, including tailored IO designs, and ESD solutions based on simulations leveraging specialized silicon ESD models.
In addition to offering fast turnaround custom IO designs, Certus offers independent ESD design, review and debug services. Through partnerships, Certus is also able to provide ESD testing & TLP support.
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Frequently asked questions about ESD Protection Library IP cores
What is 5V ESD Clamp in GlobalFoundries 180nm LPe?
5V ESD Clamp in GlobalFoundries 180nm LPe is a ESD Protection IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for globalfoundries.
How should engineers evaluate this ESD Protection?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ESD Protection IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.