How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
NTLab
Category:
DDR
1.6 Gbps DDR Programmable LVDS Transmitter/Receiver
090TSMC_LVDS_02 consists of transmitter (LVDSOUT), receiver (LVDSIN) and a bias.
Overview
090TSMC_LVDS_02 consists of transmitter (LVDSOUT), receiver (LVDSIN) and a bias. The LVDS transmitter consists of a current source (nominal 3.5mA) that drives the differential pair lines and common-mode regulator, which provides the output common-mode voltage signal equal 1.25V. The output current adjustment is defined by the digital code register ILVO<2:0>. The receiver has high DC input impedance, so the majority of driver current flows across the 100Ohm external termination resistor generating about 350mV across the receiver inputs. When the driver switches, it changes the direction of current flow across the resistor, thereby creating a valid logic state of “1” or “0”. That is, it transforms 35mV input signal to CMOS 1.8V output signal. The internal current setting is defined by digital code register ILVI<2:0>.
Key features
- TSMC 90 nm CMOS
- 1 V CMOS input logic signal
- Output current digital 3-bit adjustment (from 0.75 mA to 6.5 mA)
- 1.6 Gbps (DDR MODE) switching rates for transmitter
- Low power dissipation (1.4 mW) for receiver
- Low power dissipation (16.56 mW) for transmitter
- Conforms to TIA/EIA-644 LVDS standards
- Military temperature range: from -60 °C to + 125 °C
- Propagation delay 590 ps for transmitter
- Propagation delay 500 ps for receiver
- Internal current digital 3 bit adjustment (high inner current for high frequency, from 40 to 300 uA) for receiver
- Portable to other technologies (upon request)
Block Diagram
090TSMC_LVDS_02 block diagram
Applications
- Point-to-point data transmission
- Multidrop buses
- Clock distribution
- Backplane receiver
- Backplane data transmission
- Cable data transmission
What’s Included?
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 90nm | CIS | Silicon Proven |
Specifications
Identity
Part Number
090TSMC_LVDS_02
Vendor
NTLab
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
NTLab
HQ:
Lithuania
NTLab is a vertically integrated microelectronics design center. It has 70+ experienced and qualified engineers.
NTLab specializes in the designing of mixed-signal and RF ICs and Systems-on-Chip. It has a wide range of own silicon-verified IP blocks: processor cores, interfaces, analog and high-frequency PHYs, etc., thus allowing customized design to be fast and predictable. In-company unique combination of competences in digital, analog and RF circuits and embedded software enables NTLab to participate in the projects that require deep research and utilize most sophisticated and advanced techniques: multi-system GPS/GLONASS/Galileo/BeiDou/NavIC(IRNSS)/QZSS/SBAS navigation, RF ID, wireless communications, etc. All designed ICs are provided with test and development tools, as well as with reference software.
NTLab offers a wide range of silicon proven analog/mixed-signal IPs in 0.35µm, 0.25 µm, 0.18 µm, 0.13 µm, 0.09 µm, 65nm, 55nm, 40nm, 28nm, 22 nm CMOS and SiGe BiCMOS processes. These IPs are suitable for devices targeted both consumer and industrial markets.
Most of these IPs have been proven in silicon on the foundries: Samsung, UMC, GlobalFoundries, SMIC, VIS, Tower, X-FAB, iHP, AMS, SilTerra, STMicroelectronics, Winfoundry.
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Frequently asked questions about DDR Interface IP
What is 1.6 Gbps DDR Programmable LVDS Transmitter/Receiver?
1.6 Gbps DDR Programmable LVDS Transmitter/Receiver is a DDR IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.