UCIe (Universal Chiplet Interconnect Express)

Universal Chiplet Interconnect Express (UCIe) is an open industry standard for high-speed die-to-die interconnect communication between semiconductor chiplets within a single package. UCIe enables chip designers to combine multiple dies — potentially manufactured by different vendors and on different process nodes — into a unified System-in-Package (SiP).

The standard was launched in 2022 by a consortium of major semiconductor and technology companies including AMD, Intel, Arm, TSMC, Samsung, Qualcomm, Google, Microsoft and Meta.

UCIe is widely viewed as one of the foundational technologies enabling the transition from traditional monolithic SoCs toward modular chiplet-based architectures.

Background

As semiconductor scaling becomes increasingly expensive and reticle size limitations constrain die dimensions, the semiconductor industry has shifted toward heterogeneous integration and chiplet-based design methodologies.

Traditional large monolithic dies suffer from:

• Lower manufacturing yield
• Higher wafer costs
• Reduced design flexibility
• Long development cycles
• Process-node inefficiencies

Chiplets address these issues by partitioning a complex SoC into smaller functional dies such as:

• CPU chiplets
• GPU chiplets
• AI accelerators
• I/O dies
• Memory controllers
• Network interfaces
• Analog or RF subsystems

However, the lack of a universal interoperability standard historically limited multi-vendor chiplet ecosystems. UCIe was introduced to solve this problem by defining a common physical and protocol layer for die-to-die connectivity.

Related Articles

• 40G UCIe IP Advantages for AI Applications
• Integrating Ethernet, PCIe, And UCIe For Enhanced Bandwidth And Scalability For AI/HPC Chips
• 40G UCIe IP Advantages for AI Applications
• Multi-Die SoCs Gaining Strength with Introduction of UCIe
• PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions

Related Products

• UCIe PHY (Die-to-Die) IP
• Verification IP for UCIe
• UCIe Chiplet PHY & Controller
• D2D UCIe 1.1
• D2D UCIe 1.0

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Related Blogs

• Synopsys Advances Die‑to‑Die Connectivity with 64G UCIe IP Tape‑Out
• Cadence Tapes Out 32GT/s UCIe IP Subsystem on Samsung 4nm Technology
• UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
• The Next-Generation UCIe IP Subsystem for Advanced Package Designs
• Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process

Related News

• EXTOLL and Chip Interfaces introduce the Industry´s first Integrated UCIe IP Solution for GlobalFoundries FDX Technology
• EXTOLL announces Availability of Industry's first 16G UCIe PHY IP in GlobalFoundries 22FDX/22FDX+ Ready for Customer Integration
• GUC Announces Tape-out of UCIe 64G IP on TSMC N3P Technology
• SkyeChip’s UCIe 3.0 Advanced Package PHY IP for SF4X Listed on Samsung Foundry CONNECT
• YorChip and Sofics Expand UCIe PHY Across TSMC Nodes