Universal NVM Express Controller (UNEX)

The Universal NVM Express Controller (UNEX) is highly flexible and configurable design targeted for both Enterprise and client class solutions that unlock the current and future potential of PCIe-based SSDs. The UNEX controller core efficiently supports multi-core architectures ensuring thread(s) may run on each core with their own queue and interrupt without any locks required. It provides support for end-to-end data protection, security and encryption as well as robust error reporting and management capabilities. The controller architecture is carefully tailored to optimize link and throughput utilization, latency, reliability, power consumption and silicon footprint.

The UNEX controller can be used along with the LDPC, DDR4/3 (UMMC) and Enterprise Flash controller (EFC) IPs for a complete NVMe/SSD implementation.

The UNEX controller comes with 3rd flavors part:

• Native UNEX Controller with proprietary control and Data path interfaces
• UNEX Controller with AXI Control and Data path interfaces for easy adoption in an SoC implementation
• UNEX Controller with Streaming Control and Data path interface (AXI4 ST) for easy adoption in an SoC implemen tation with PCIe HIP or any third party PCIe Controllers

UNEX Controller design is independent of implementation tools and target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally.

Configurable Options

• Multi-port or Single Port
• Inclusion / Exclusion of AXI / Streaming interface modules
• Number of IO Queues
• IO Queue Depth
• Number of DMA Engines
• Number of Non-Volatile Memory Channels
• Data Path Width (64, 128, 256, 512)
• Data Buffer Size

Design Attributes

• Highly modular and configurable design
• Layered architecture
• Fully synchronous design
• Supports both sync and async reset
• Clearly demarked clock domains
• Software control for key features
• Multiple loopbacks for debug

• Compliance to NVM Express 2.0 Specification
• Compliant with AXI4-ST/AXI Interface towards PCIe interface 
• Compliant with AXI4 interface towards memory subsystem interface 
• Internal data path width: 128/256/512 bit 
• Host memory page size support of 128 MB 
• Support for round robin or weighted round robin with urgent priority arbitration Mechanism 
• Supports for configurable number of IO queues 
• Supports all optional admin commands 
• Supports all optional NVM commands 
• Supports Multipath IO and namespace sharing capabilities End-to-end Data protection support 
• Supports Multiport Configuration for Multipath IO Support 
• Supports for configurable queue depth 
• Configurable number of DMA Engines
•  Efficient and streamlined command handling
•  Well defined command interface for local CPU to perform sub system initialization and to handle all non-hardware  
• Support for Zoned namespace command set and Key Value command set
•  E2E protection(16b / 32b / 64b) Support 
• Supports Copy command and Lock Command  

• Superior architecture-optimized for high performance, low latency, low power and low gate count
• Feature rich, highly flexible, scalable, configurable and timing friendly design
• Ease of integration
• Verified with leading VIP

• RTL Code
• UVM-based test bench and behavioral models
• Test cases
• Protocol checkers, bus watchers and performance monitors
• Configurable synthesis shell
• NVM Device FW Stack
• FPGA Netlist for Prototype