Overview
Tessent Embedded Analytics accelerates debug, validation, and optimization of complex multi-core SoCs. Leveraging embedded non-intrusive instrumentation such as bus monitors, NoC monitors, and CPU debug modules, debug and software engineers can observe what’s happening in the design when operational software is running on the system. The instruments enable full transaction-level visibility of traffic on buses with a wide range of measurements, analytics and statistics gathering. All of these are highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering.
All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.
Learn more about Debug Trace IP core
On-chip analysis can effectively improve our understanding of complex embedded systems, such as Open Core Protocol (OCP)-based architectures. For OCP level systems integration, real-time performance analysis is often a priority for getting products to market quickly, and embedded instrumentation analysis that can be used with emulators, prototypes, and production silicon can provide systems information and control that go beyond simulation based analysis
Today we present to you the Akeana 1000 Series Processors, a series of High Performance processors IP which is optimized for AI applications and workloads, thus providing a quick AND efficient processing solution for your AI needs.
With a promise to revolutionize our driving experience, automotive displays are evolving at an unprecedented pace. In modern vehicles, the digital dashboard with a variety of displays that provide access to all driver controls has replaced the physical mechanisms and panels.
Today, Imagination is launching its latest product: Imagination DXTP, a new GPU IP which extends battery life when accelerating graphics and AI workloads on smartphones and other power constrained devices.
The rise of opensource RISC-V CPU Instruction Set Architecture (ISA) has led many developers to consider migrating from existing popular computer architectures like x86, Arm, MIPS and more to RISC-V CPU ISA. This transition offers various advantages, including an open-source framework and extensive community support.
Robert Chyla, MIPS
