Vendor: Exostiv Labs Category: Debug Trace

Deep capture / high visibility Debug IP for Intel FPGA

The customizable EXOSTIV IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design with…

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Overview

The customizable EXOSTIV IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design without having to store the full trace data in the FPGA. The EXOSTIV IP core uses the FPGA transeivers as a high bandwidth channel to an external memory (in EXOSTIV Probe). The IP includes many advanced features for extending visibility on FPGA running at speed of operation- including data group definition and multiplexing, boolean trigger equations, data qualification (data filtering) and edge transition triggers. Because EXOSTIV IP core is synchronous to the design being monitored, all design clock constraints that are applied to your design are also applied to the components inside IP Core. EXOSTIV IP is at RTL level thanks to IP templates and constraints automatically generated at IP setup.

Key features

  • Configurable upstream link, up to 4 transceivers at 12.5 Gbps each.
  • Downstream link to configure IP triggers and data group selection without the need to re-implement the instrumented design.
  • Up to 16 configurable 'Capture Units'
  • Up to 16 multiplexed Data Groups per Capture Unit
  • Up to 2,048 nodes per Data Group
  • Up to 32k simultaneously observable nodes
  • Multi-clock domain support
  • Cross-capture unit trigger lines

Block Diagram

EXOSTIV IP for Intel FPGA block diagram

Benefits

  • Extreme visibility on FPGA running at speed of operation
  • Efficient use of FPGA resources: the size of the IP memory in the FPGA does not grow with the size of the capture.
  • Extended visibility over time: the capture can span to hours of real FPGA operating times, from start to end (interrupted capture mode)
  • Real-world visibility level with a total of 8 GB of trace for a single capture.

Applications

  • FPGA debug and verification

What’s Included?

  • Complete FPGA debugging solution, including EXOSTIV Dashboard software (Linux, Windows) for EXOSTIV IP setup and insertion - and for EXOSTIV IP control for trace data extraction at run-time.
  • Includes EXOSTIV Probe for data extraction from target FPGA at run-time.
  • Includes terabyte-capable Myriad waveform viewer.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
EXOSTIV IP for Intel FPGA
Vendor
Exostiv Labs
Type
Silicon IP

Provider

Exostiv Labs
HQ: Belgium
Exostiv Labs provides solutions to debug FPGA running at speed of operation with maximal visibility. The company's debug IP cores coupled with its probe and software solutions aim at reducing the total time spent on FPGA debug and thereby shortening the total time to market for its users. Exostiv Labs' solutions address both the needs of ASIC / SoC companies using FPGA for prototyping and of OEM manufacturers using FPGA technologies in their products.
Contact Exostiv Labs

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Frequently asked questions about Debug Trace IP

What is Deep capture / high visibility Debug IP for Intel FPGA?

Deep capture / high visibility Debug IP for Intel FPGA is a Debug Trace IP core from Exostiv Labs listed on Semi IP Hub.

How should engineers evaluate this Debug Trace?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Debug Trace IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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