Vendor:
Logic Design Solutions
Category:
SPI / QSPI XSPI
Serial protocol Interface Slave
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master.
Overview
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master. The MSPIS IP can be programmed to run either in standard SPI mode where bidirectional one byte transactions are implemented, or in extended SPI mode where frame transactions are implemented through 14-bits address and 16 or 32-bits data. The MSPIS IP controls all SPI-bus specific sequences, protocol and timing. This IP can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.
Key features
- Single-chip synchronous SPI Slave IP in FPGA
- Designed to be included in high-speed and high-performance applications
- Direct Connection to CPU register set
- High frequency rate
- Two run-time mode : Standard SPI mode and Extended SPI mode
- Synchronised on system clock
- Serial clock programmable with polarity and phase
- FPGA speed grade operating frequency dependant : system clock up to 220 MHz
- Available in VHDL source code format for ease of customization
- Can be customised by Logic Design Solutions
What’s Included?
- VHDL Source code
- VHDL Test Bench for behavioural and gate level simulation.
- Data Sheet and Reference Guide
- User’s guide : Simulation, Synthesis and Place and Route procedures.
- Constraint File
- DO254 documentation available on request.
Specifications
Identity
Part Number
MSPIS
Vendor
Logic Design Solutions
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
Logic Design Solutions
HQ:
FRANCE
Logic Design Solutions is an FPGA Design and Intellectual Property (IP) company that provides Design Services, IP (cores) and DO254 methodology to FPGA customers.
We engage ourself to be your high standard quality solutions provider for FPGA cores and Design Services.
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Frequently asked questions about SPI / QSPI / xSPI IP cores
What is Serial protocol Interface Slave?
Serial protocol Interface Slave is a SPI / QSPI XSPI IP core from Logic Design Solutions listed on Semi IP Hub.
How should engineers evaluate this SPI / QSPI XSPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.