Secure OTP
Data protection from safeguarded anti-fuse OTP memory Secure OTP is a combined Physical Macro, and Digital RTL providing comprehe…
Overview
Data protection from safeguarded anti-fuse OTP memory
Secure OTP is a combined Physical Macro, and Digital RTL providing comprehensive data protection. It is the ultimate solution for embedded Non-Volatile Memory in CMOS logic or logic-derived technologies. The RTL part provides glue logic of the OTP/PUF controller, tamperproof features, and standard AMBA interfacing. Secure OTPs tailored design maximizes efficiency and allows simplified integration across multiple emerging IC markets and ASIC applications. It is available in various densities and configurations with several CMOS technologies, delivering an embedded non-volatile memory with outstanding reliability and performance.
Secure OTP includes a 1024-bit Physical Unclonable Function (PUF), which is used for physical address scrambling and IO shuffling to enhance stored data security. It is a pure hardware PUF with a virtually ideal entropy that doesn’t require any helper data for error correction, allowing access within a few microseconds.
Secure OTP leads the field in terms of enhanced security OTP platform availability. Through PUFsecurity’s parent company, eMemory, we draw from over 20 years of experience partnering with foundries and delivering high-quality IPs.
Today, the rising security risks to IoT devices are limiting the market’s potential. The answer is creating a collaborative security ecosystem that draws from the safest Hardware, Software, and Operating System solutions. Secure OTP can become the bedrock of any chip security ecosystem and protect critical data such as the root key and the boot code.
Key features
- Up to 128kb mass production OTP with built-in instant hardware encryption (customization available)
- Comprehensive anti-tamper designs in physical and RTL
- APB control interface with secure/non-secure access privilege
- Four 256-bit hardware PUF fingerprints for scrambling drop-in-use Secure OTP Storage
- Comprehensive permission, zeroization, and lock mechanism to enhance product lifecycle management and protection
- Software stack of Firmware and API
- Autoload: Automatically send trim parameters from OTP upon power-up.
- Secure Boot: Ensure the device only boots up with the authenticated software.
- Process Availability
- Scalable down to 3nm, with continuous development
- Available across worldwide foundries
- Security Features
- Riscure certified
- Resistant to physical attacks, including decapsulation, microscope imaging, probing, reverse engineering, etc.
- PUF-based Secure Storage
- Up to 128Kb OTP
- Various memory maps configurations to fulfill different usage scenarios
- Scrambler based on PUF value ensures secure data storage, unique to each chip
- Unique scramble value per chip, making the stored information in each chip different from each other
- Stored values cannot be changed/deleted
- Controller/Interface
- APB or AHB System Bus Interface
- APB or TCM Crypto Bus Interface
- Secure OTP Wrapper (Factory test, user, RMA debug, Read/Write, Read-Only, and Non-accessible modes)
- Autoload interface for system calibration upon powers on to support product LFM, secure boot, secure debug, etc..
- IEEE1687 JTAG testing interface
- Optional XiP package available
- Memory Built-In Self Repair/Test Data Register/Secure Debug access through external Test Access Port
Block Diagram
Applications
- Secure OTP safely stores sensitive data such as keys and boot code.
- In addition, its universal integration and wide availability make it suitable for use across multiple ASIC and SoC applications in, for example, SSD controllers, DPUs, WiFi, PCIe, STB, and Smart TVs.
What’s Included?
- Datasheet
- Release Notes
- Integration Guidelines
- Timing .lib File
- LEF
- GDS Phantom File
- Verilog HDL File (Behavior Model)
- Verilog HDL File (FPGA)
- Application Note
- Reference Scripts
- Reference API/FW Libraries
- Hard Macro Release Note
- Test Methodology
- Testbench
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about eFuse / OTP IP core
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Frequently asked questions about eFuse / OTP IP cores
What is Secure OTP?
Secure OTP is a eFuse / OTP IP core from PUFsecurity listed on Semi IP Hub.
How should engineers evaluate this eFuse / OTP?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this eFuse / OTP IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.