Vendor: Synopsys, Inc. Category: eFuse / OTP

NVM OTP XBC TSMC N5 1.2V

Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs.

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Overview

Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs. Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges. Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries.

Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7. Synopsys OTP in TSMC N5A is Grade-1 qualified to AEC-Q100 standard

Synopsys OTP NVM offers non-volatile storage for configuration, trimming, calibration, and encryption keys with the Base Capacity OTP product (XBC OTP), code storage with the High-Capacity OTP product (XHC OTP), and secure storage with the Secure Code OTP product (XSC OTP).

Synopsys OTP XBC IP is Automotive Grade 1 AEC-Q100 Qualified and is delivered with ISO 26262 functional safety deliverables for random hardware faults, reducing risk, accelerating AEC-Q100 product-level qualification, and meeting the stringent quality requirements for automotive SoCs.

Synopsys OTP NVM IP

Available in standard CMOS processes, Synopsys OTP IP does not require any additional mask layers or process steps and provides an alternative to mask ROM, eFuse and embedded Flash memory.

Synopsys OTP NVM IP addresses the power, form factor and security requirements of a broad range of applications, including code storage, encryption keys, analog trimming, and IC configuration in Power Management ICs (PMICs), Sensors, Home Entertainment, Automotive, Industrial, Mobile, Mil/Aero and IoT products.

Key features

  • Anti-fuse OTP ensure security, scalability, and reliability
  • Automotive AEC-Q100 Grade-1 qualified and with ISO 26262 functional safety deliverables for random hardware faults
  • Optimized for area, programming time, and power
  • High level of security prohibits memory content modification
  • Flexible, field-programmable memory
  • Built-in error correction schemes available
  • Comprehensive manufacturing built-in test features available

Block Diagram

dwc_nvm_ts05n03sxxxxxhxbcxxxi block diagram

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Specifications

Identity

Part Number
dwc_nvm_ts05n03sxxxxxhxbcxxxi
Vendor
Synopsys, Inc.

Provider

Synopsys, Inc.
HQ: USA
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
Contact Synopsys, Inc.

Learn more about eFuse / OTP IP core

Why Hardware Root of Trust Needs Anti-Tampering Design

The hardware root of trust (HRoT) provides the trust base (root key), hardware identifier (UID), hardware unique key (HUK), and entropy required for the secure operation of the entire chip and therefore is often the focus of hacker attacks. If the design can’t effectively resist attacks, hackers can easily obtain the secrets of the entire chip. Attackers can use the secrets to crack identity authentication and data encryption and steal product design know-how, causing application security problems.

Optimizing Sensor Performance with 1T-OTP Trimming

A sensor is a device that detects a change in a stimulus and converts it into an electronic signal that can be measured or recorded. The stimulus can be many things, including a physical property, environmental parameter, chemical composition or a location, to name just a few. All sensing elements have nonlinearities that include an intrinsic nonlinearity over sensing range along with offset and sensitivity nonlinearity variations over temperature.

Solving Chip Security's Weakest Link

With the invention of Physical Unclonable Functions (PUF), we can now create a unique, inborn, unclonable key at the hardware level. The natural follow-up question to this is, “but how do we protect this key?” It is like storing your key to secrets in a drawer, a surefire way to break the secure boundary and create vulnerabilities.

Securing Smart Connected Homes with OTP NVM

The market for piracy is huge and hackers have become increasingly sophisticated even when security is implemented in hardware. The race between the aggressors and protectors is a battle without end. Smart connected home devices are increasingly storing and processing very sensitive and private user data in addition to attempting to deliver copyright protected content from service providers. Protecting consumer data is vital.

I-fuse: Most Reliable and Fully Testable OTP

Patented by Attopsemi™, I-fuse™ is a revolutionary non-breaking fuse technology that can be reliably programmed by heat assisted electromigration below a break point. Any cell can be tested as programmable if the initial fuse resistance is low enough (e.g. <400 ohms) to generate enough heat for programming.

Frequently asked questions about eFuse / OTP IP cores

What is NVM OTP XBC TSMC N5 1.2V?

NVM OTP XBC TSMC N5 1.2V is a eFuse / OTP IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this eFuse / OTP?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this eFuse / OTP IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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