Ldpc decoder IP

Compare 87 IP from 19 vendors (1 - 10)

LDPC Decoder for 5G NR and Wireless
- The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
- It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
- The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.
(2048,1723) LDPC decoder for IEEE 802.3an 10GBASE-T
- Strong error correction performance
- Optimized method significantly lower the error floor at minimal cost
- High throughput with low complexity hardware
- Early termination technique
IEEE 802.11 n/ac/ax LDPC Decoder
- LDPC Decoder, support all IEEE 802.11 n/ac/ax defined block lengths (648, 1296, 1944) and code rates (1/2, 2/3, 3/4 and 5/6).
CCSDS Rate 1/2 TC and TM LDPC Decoder
- CCSDS TC and TM compatible
- Rate 1/2
- Data lengths of TC 64 and 256 or optional TM 1024 bits
- Includes ping-pong input and output memories
LDPC Decoder for 802.11
- Soft decision decoding
- IEEE 802.11n/ac/ax standard compliant
- Throughput matching the required specifications.
IEEE802.11n/ac/ax Wi-Fi LDPC Decoder and Encoder - silicon proven
- High throughput design.
- Frame-to-frame on-the-fly configuration.
Nonbinary LDPC Decoder
- Regular parity check matrix
- Soft decision SPA decoding
- Supports different code sizes
- Hard decision output
DVB-C2 LDPC Decoder IP
- Irregular parity check matrix
- Layered Decoding
- Minimum sum algorithm
- Configurable number of iterations
DVB-S2 LDPC Decoder IP
- Irregular parity check matrix
- Layered Decoding
- Minimum sum algorithm
- Configurable number of iteration
DVB-T2/Lite LDPC Decoder IP
- Irregular parity check matrix
- Layered Decoding
- Minimum sum algorithm
- Configurable number of iteration

LDPC Decoder IP