Vendor: SmartDV Technologies Category: MRAM / RRAM

RERAM Memory Model

RERAM Memory Model provides an smart way to verify the RERAM component of a SOC or a ASIC.

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Overview

RERAM Memory Model provides an smart way to verify the RERAM component of a SOC or a ASIC. The SmartDV's RERAM memory model is fully compliant with standard RERAM Specification and provides the following features. Better than Denali Memory Models.

RERAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

RERAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports RERAM memory devices from all leading vendors.
  • Supports 100% of RERAM protocol standard.
  • Supports all the RERAM commands as per the specs.
  • Supports Serial peripheral Interface (SPI).
  • Supports data retention without using a back-up battery.
  • Supports upto 4 Mbits (524,288 Words x 8bits).
  • Supports 1.2 x 10^6 rewrite operations.
  • Supports 256 bytes write buffer size.
  • Supports resistive-variable Memory.
  • Supports up to 5 MHz (Max) Operating frequency.
  • Supports Data endurance up to 1.2 x 10^6 times/byte.
  • Supports Data retention up to 10 years.
  • Supports WIP Polling.
  • Supports Block Protection.
  • Supports for all types of timing and protocol violation detection.
  • Protocol checker fully compliant with RERAM Specification.
  • Constantly monitors RERAM behavior during simulation.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Block Diagram

RERAM Memory Model block diagram

Benefits

  • Faster testbench development and more complete verification of RERAM designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the RERAM testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
RERAM Memory Model
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about MRAM / RRAM IP cores

What is RERAM Memory Model?

RERAM Memory Model is a MRAM / RRAM IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this MRAM / RRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MRAM / RRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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