Overview
The Synopsys Foundation IP optimized for the TSMC’s 22nm Ultra Low Leakage (ULL) process provides designers an extensive offering of high-speed,
high-density, ultra-high density, and eMRAM compilers, logic libraries, and GPIO solutions that are extensively proven in silicon, reducing project risk, and speeding time-to-market.
Built-in power management advanced features Synopsys Foundation IP on TSMC 22ULL process enables SoC designers to explore power, performance and area (PPA) tradeoffs to generate optimal memory configurations. It includes duet packages of embedded memories and logic libraries with standard cells, SRAMs, register files, ROMs, High-Performance Core (HPC) Design Kits, and Power Optimization Kits (POKs)—all the foundation IP elements needed to design ultra- low power SoCs (Figure 1). The integrated STAR Memory System (SMS) enables the test and repair of embedded memories, delivering high test quality and
yield while lowering overall chip area. Synopsys Foundation IP for TSMC 22ULL process includes 1.8V/3.3V GPIO with 1.8V/3.3V Tolerant and Failsafe operation and the complete hardened 1.8V/3.3V SD/eMMC PHY solution compliant with eMMC 5.1 and SD v6.0.
Synopsys Foundation IP for TSMC 22ULL solution enables designers of consumer, mobile, IoT, AIoT and automotive applications that require high speed, low leakage, and low power to achieve the best combination of PPA for their SoC designs.
Learn more about MRAM / RRAM IP core
This article will explore the potential advantages of RRAM and MRAM in various applications and elucidate why such new technologies are imperative to address future memory demands, as well as some challenges designers may encounter in the implementation.
Amir Regev, Weebitnano
In this article, a new way to implement high performance data storage is presented, allowing the use of server-class storage technology in an embedded environment.
Most of SSD manufacturers jumped into this new storage market with flash-based technology. A second wave of products will come in the near future, using a new generation of non-volatile memories, delivering impressive speed performances compared to NandFlash memories. The SSD manufacturers will have to deal with low latency SSD controller design in order to benefit from the new NVM features, while keeping high reliability and low power consumption.
This white paper proposes a solution based on a full hardware NVMe implementation, describing its architecture, implementation and characterization.
Embedded flash and its off-chip counterpart, NOR flash, have been the gold standards for non-volatile memory — the kind used for persistent or long-term data storage — for many years.
Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devices. Nonvolatile memory (NVM) devices offer one such attractive alternative with ∼2× density and data retention after powering off. Compute-in-memory (CIM) architectures further improve energy efficiency by fusing the computation operations with AI model storage. Electronic characteristics of NVM devices, like resistance in the two resistance states, directly affect the circuit designers’ decisions and result in the varying performance of NVM-CIM chips.
