Quad SPI Controller

The SPI (Serial Peripheral Interface) is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes:

• Register mode: SPI sends and receives by configuring the corresponding registers.
• DMA mode: SPI DMA interface uses a stream pre-processing protocol to ease the construction of SPI transfers combining commands and data stream.
• XIP memory-mapped mode: the external Flash memory is mapped to the device address space and is seen by the system as if it was an internal memory.

• The SPI controller support master/slave operation over the single-lane, dual-lane,quad-lane and half duplex singlelane protocols
• Programmable clock polarity and phase (CPOL/CPHA)
• Configurable MSB First or LSB First
• Master/Slave mode configurable frequency (FPCLK/2 max)
• SPI bus busy status flag
• The baseline controller provides a FIFO-based interface for performing programmed I/O. Software initiates a transfer by enqueuing a frame in the transmit FIFO; when the transfer completes, the slave response is placed in the receive FIFO
• The dedicated SPI controller implements a SPI flash read/write sequencer. The SPI controller is reset to a state which allows memory-mapped reads
• SPI uDMA interface uses a stream pre-processing protocol to ease the construction of SPI transfers combining commands and data stream
• Buffer or FIFO size for RX and TX configurable at RTL level
• SDR and DDR support
• Configurable SCK sample points for DDR mode