Synopsys Tapes Out SLM PVT Monitor IP on TSMC N5 and N3E Processes
Rohan Bhatnagar, Staff Product Manager, Synopsys EDA Group
Vendor:
Agile Analog
Category:
PVT Monitor
PVT Sensor Subsystem
The agilePVT Sensor Subsystem is a low power integrated macro consisting of Process, Voltage, and Temperature sensors, and associ…
Overview
The agilePVT Sensor Subsystem is a low power integrated macro consisting of Process, Voltage, and Temperature sensors, and associated reference generator, for on-chip monitoring of a device's physical, environmental, and electrical characteristics. The monitoring of process, voltage and temperature variations are critical to optimize power and performance for modern SoCs/ASICs, especially for advanced node and FinFET processes.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.
Key features
Temperature Sensor
- Measurement range: -40oC to +125oC
- Accuracy (Uncalibrated) +/-5°C
- Accuracy (Calibrated)
- -20°C to +100°C = +/-2°C
- 0°C to +50°C = +/-0.5°C
Voltage Sensor
- Accuracy (Uncalibrated) 50mV
- Accuracy (Calibrated) 10mV
Process Sensor
- In-chip monitoring of process variation
- Ring oscillator-based design to suit application requirements
- Scan-enabled to provide testability
agilePVT Subsytem
- Start-up time: Typ 20us
- Current consumption: Max 25uA
- Industry standard digital interface
- Fully integrated macro
- Standard AMBA APB interface
Block Diagram
agilePVT block diagram
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
agilePVT
Vendor
Agile Analog
Provider
Agile Analog
HQ:
United Kingdom
Agile Analog is transforming the world of analog IP with Composa™, its innovative, configurable, multi-process analog IP technology. Headquartered in Cambridge, UK, with a growing number of partners and customers across the globe, Agile Analog has developed a unique way to automatically generate analog IP that meet the customer’s exact specifications on almost any process from any foundry. The company provides a wide and ever expanding selection of analog IP and subsystems for power management, data conversion, IC health and monitoring, security and always-on domains. Agile Analog's novel approach utilises tried and tested analog circuits within its Composa library to create customised and verified analog IP solutions. This reduces the time to market and increases quality, helping to accelerate innovation in semiconductor design.
Learn more about PVT Monitor IP core
The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
At the recent IPSoC Conference in Silicon Valley, Rohan Bhatnagar gave a talk on the growing importance of PVT Monitoring for effective SLM. Rohan is the product manager for Synopsys’s SLM PVT Monitor IPs. A synthesis of the salient points from his talk follows.
Let's Talk PVT Monitoring: AVS & DVFS
Let's Talk PVT Monitoring: Process Detection & Variability
Let's Talk PVT Monitoring: Supply Monitoring on 28nm & FinFET - The Challenges Posed
Let's Talk PVT Monitoring: Thermal Issues Associated with Modern SoCs - How Hot is Hot?
Ramsay Allen
Frequently asked questions about PVT Monitor IP cores
What is PVT Sensor Subsystem?
PVT Sensor Subsystem is a PVT Monitor IP core from Agile Analog listed on Semi IP Hub.
How should engineers evaluate this PVT Monitor?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PVT Monitor IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.