Provider
Dolphin Technology
HQ:
USA
Dolphin Technology provides SoC designers with a broad array of silicon-proven IP for Memory, I/O, Standard Cells, DDR PHY, Memory Controllers, PLL/DLL and Memory Test and Repair (BIST).
Dolphin offers both standard and custom solutions that are optimized for low power, high performance and high density across a broad range of process technologies. These solutions include:
- Memory Compilers (Single & Dual Port SRAM, 1 & 2 Port RF, ROM)
- Specialty Memory (ROM, BCAM, TCAM, CAM)
- I/O (General purpose, bus-specific, DDR, Flash)
- Standard Cell libraries (7-track, 10-track, 12-track, 14-track)
- DDR PHY (hardened DDRx & LPDDRx SDRAM PHY)
- PLL/DLL (programmable PLL, fully digital DLL)
- SERDES
- Memory Controllers (DDRx & LPDDRx DRAM)
- Memory BIST
- And more...
Dolphin Technology has been enabling SoC design teams to enhance quality and reduce time to market since 1996.
Learn more about Power Management Controller IP core
This article shows several ways to implement a power management controller using the new PMBus Revision 1.3 specification, and addresses several new considerations with architecting a system using this new specification.
Rivos is pleased to announce the successful secure provisioning of the integrated OpenTitan open source Root of Trust (RoT) in its SoC. This was done during the chip production process using the ZeroRISC provisioning appliance and platform.
Seven Steps to Create a Formal IP Specification
The USB 3.1 spec supports data rates up to 10 Gbits/second but poses new hurdles in link-layer design for chip designers, says an expert in the IP group at Synopsys.
The latest PCIe 6.x specification brings groundbreaking advancements in power efficiency and performance optimization. In this technical demonstration, Senior Principal Application Engineer Julien Eydoux showcases two features of Rambus’ PCIe 6.x Controller: L0p mode and FLIT mode operation.
This paper details first PCIe errors, error logging and then the error handling on a typical SoC.