Programmable gain amplifier
250iHP_PGA_01 is a programmable gain amplifier (PGA) with low-pass filter (LPF).
Overview
250iHP_PGA_01 is a programmable gain amplifier (PGA) with low-pass filter (LPF). The block consists of 2 amplification stages with tunable (5-bit control) gain from 0 to 40dB. Both stages have single-ended input and output and produce max 20dB gain each. Gain can be set by the digital code GC<4:0>. Internal LPF is targeting 15 kHz cut-off frequency. Cut-off frequency adjustment can be held by changing of BW1<3:0> and BW2<3:0> inputs for 1st and 2nd amplifiers respectively. DC offset adjustment can be held by setting of OFFSET1<3:0> and OFFSET2<3:0> inputs. The IP features are low power consumption and compact area.
Key features
- iHP SG25H4 SiGe BiCMOS 0.25 um
- 2.5 V supply voltage
- Gain range 0…40 dB (5-bit control)
- Low current consumption: 0.5mA
- Compact die area: 0.373 mm2
Block Diagram
Applications
- AGC systems
- Gain control systems
- Receivers
What’s Included?
- Schematic or NetList
- Abstract view (.lef and .lib files)
- Layout (optional)
- Verilog behavior model
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Amplifier IP cores
What is Programmable gain amplifier?
Programmable gain amplifier is a Amplifier IP core from NTLab listed on Semi IP Hub.
How should engineers evaluate this Amplifier?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Amplifier IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.