Vendor: NTLab Category: Single-Protocol PHY

Programmable CMOS LVDS Transmitter/Receiver

LVDS device consists of one common bandgap reference voltage generator, a number of LVDS transmitter pad groups with their bias b…

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TSMC 130nm BCD+ View all specifications

Overview

LVDS device consists of one common bandgap reference voltage generator, a number of LVDS transmitter pad groups with their bias blocks, and a number of LVDS receiver pad groups (whether rail to rail or reduced input range) with their bias blocks. Also, LVDS transceiver pad groups may be used. In this case, the receiver bias and the transmitter bias blocks should be instantiated for each transceiver pad group. Group size is defined by the corresponding bias output dimension. In the case when desired group size is not the power of 2, several bias blocks should be used, or bias block with size larger than the group size can be instantiated. For example (see fig 1.), to create 6 RX LVDS lines and 30 TX LVDS lines, one LVDSBIASRX4X, one LVDSBIASRX2X, and one LVDSBIASTX32X cells can be instantiated. Two current lines of the LVDSBIASTX32X cell (that are not connected to the LVDS TX pads) should be left open. For the layout design, it is recommended to place bias blocks as close as possible to their corresponding receiver, transmitter, or transceiver pads. It should be noted that all pad cell ground pins in a group, and the corresponding bias block ground pin should be connected together. However, bandgap reference block ground may be connected to the different ground net, as well as different pad groups may utilize different ground nets.

Key features

  • TSMC 0.13 um CMOS
  • 3.3 V analog power supply
  • 1.2 V digital power supply
  • 1.2V CMOS input and output logic signals
  • 8-step (3-bit) adjustable transmitter output current (range from 0.75 mA to 6.5 mA)
  • 1.25 Gbps (DDR MODE) switching rates
  • Conforms to TIA/EIA-644 LVDS standards without hysteresis
  • Two receiver cell types: rail to rail and reduced input range
  • Temperature range: -40 °C to + 125 °C
  • Optimized for pad-limited layout design
  • Portable to other technologies (upon request)

Block Diagram

130TSMC_LVDS_04 block diagram

Applications

  • Point-to-point data transmission
  • Multidrop buses
  • Clock distribution
  • Backplane receiver
  • Backplane data transmission
  • Cable data transmission

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Silicon Options

Foundry Node Process Maturity
TSMC 130nm BCD+ —

Specifications

Identity

Part Number
130TSMC_LVDS_04
Vendor
NTLab
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

NTLab
HQ: Lithuania
NTLab is a vertically integrated microelectronics design center. It has 70+ experienced and qualified engineers. NTLab specializes in the designing of mixed-signal and RF ICs and Systems-on-Chip. It has a wide range of own silicon-verified IP blocks: processor cores, interfaces, analog and high-frequency PHYs, etc., thus allowing customized design to be fast and predictable. In-company unique combination of competences in digital, analog and RF circuits and embedded software enables NTLab to participate in the projects that require deep research and utilize most sophisticated and advanced techniques: multi-system GPS/GLONASS/Galileo/BeiDou/NavIC(IRNSS)/QZSS/SBAS navigation, RF ID, wireless communications, etc. All designed ICs are provided with test and development tools, as well as with reference software. NTLab offers a wide range of silicon proven analog/mixed-signal IPs in 0.35µm, 0.25 µm, 0.18 µm, 0.13 µm, 0.09 µm, 65nm, 55nm, 40nm, 28nm, 22 nm CMOS and SiGe BiCMOS processes. These IPs are suitable for devices targeted both consumer and industrial markets. Most of these IPs have been proven in silicon on the foundries: Samsung, UMC, GlobalFoundries, SMIC, VIS, Tower, X-FAB, iHP, AMS, SilTerra, STMicroelectronics, Winfoundry.
Contact NTLab

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Frequently asked questions about Single-Protocol PHY IP

What is Programmable CMOS LVDS Transmitter/Receiver?

Programmable CMOS LVDS Transmitter/Receiver is a Single-Protocol PHY IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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