High-Performance Memory Expansion IP for AI Accelerators
AI inference performance is increasingly constrained by memory bandwidth and capacity - not compute.
- Data Compression
High-Performance Memory Expansion IP for AI Accelerators
AI inference performance is increasingly constrained by memory bandwidth and capacity - not compute.
The Cache MX IP compresses on-chip L2, L3 SRAM cache enabling 2x effective capacity.
High performance and low latency hardware accelerated zram/zswap at unmatched power efficiency
The SuperRAM implements a hardware accelerator for zram compression and decompression.
Up to 50% main memory bandwidth acceleration
The Ziptilion Bandwidth IP accelertes the main memory bandwidth with up to 50%.
AES-XTS encryption/decryption IP
SphinX is designed to accommodate the speed, latency and throughput requirements of high performance computer systems main memory…
The Flash MX IP Core implements a hardware accelerator for zstd compression and decompression.
DenseMem increases effective CXL Type 3 Device memory capacity by a factor of 2x through transparent, in-line memory compression/…