Vendor:
ElectraIC
Category:
Post Quantum
KYBER IP Core
Kyber IP is a core designed for Kyber post-quantum Key Encapsulation Mechanism (KEM).
Overview
Kyber IP is a core designed for Kyber post-quantum Key Encapsulation Mechanism (KEM). It currently supports the Encapsulation and Decapsulation functions, with key generation functionality planned for future implementation. This IP is fully compliant with the Kyber specification submitted during Round 3 of the NIST Post-Quantum Cryptography Standardization process. Additionally, Kyber IP will be enhanced in the future to achieve compliance with ML-KEM (FIPS-203).
Key features
- supports encapsulation and decapsulation operations
- supports all modes K=2,3,4.
- is compliant with Kyber specification round 3.
- has fully stallable input and output interfaces.
- Key generation feature is going to be implemented in the near future.
Block Diagram
EIP-18009 block diagram
What’s Included?
- Encrypted Netlist
- Synthesis Scripts
- Comprehensive Documentation
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
EIP-18009
Vendor
ElectraIC
Type
Silicon IP
Security
Crypto Algorithm
CRYSTALS-Kyber (ML-KEM)
Provider
ElectraIC
HQ:
Turkey
ElectraIC provides electronic circuit design and verification services in the field of ASIC, FPGA and embedded systems. The team has the experience of working with global multinational companies. The company has been involved in and continues to take part in many projects, especially in Aerospace and Defense areas, as well as consumer electronics. Functional safety using DO-254, ISO 26262 and EN 50129 are speciality areas. ElectraIC delivers also trainings on ASIC, FPGA and embedded systems.
Contributions ElectraIC can make to your organization:
- Design IP Cores
- Design & Verification Services: ASIC / FPGA and Embedded Systems’ development
- Functional Safety Consultancy & Training Services
- Trainings: Wide range of trainings with more than 150 different trainings
Learn more about Post Quantum IP core
How to design secure SoCs Part IV: Runtime Integrity Protection
SoC designers are increasingly challenged to integrate robust security measures into their designs. Modern connected devices, such as automotive Electronic Control Units (ECUs), Internet of Things (IoT) nodes, and industrial control systems, face increasing susceptibility to cyberattacks. This escalating threat landscape underscores the critical importance of mandatory security requirements.
Nine Compelling Reasons Why Menta eFPGA Is Essential for Achieving True Crypto Agility in Your ASIC or SoC
Today’s world is already overly complicated to provide robust product security, with extremely motivated hackers creating novel threats exposing new vulnerabilities every day. But considering tomorrow’s world with the looming threat of quantum computing, expanding AI possibilities and rapidly evolving regional regulations and export control risk with severe financial penalties, this is a daunting challenge.
Deploying StrongSwan on an Embedded FPGA Platform, IPsec/IKEv2 on Arty Z7 with PetaLinux and PQC
The objective of this article is to present and analyze a concrete IPsec/IKEv2 deployment on an FPGA-based embedded Linux system. Using an Arty Z7 FPGA platform with PetaLinux and StrongSwan, the focus is on system-level integration rather than protocol theory: how the IPsec stack is built and deployed, how classical and post-quantum key exchange are integrated without modifying standardized protocols, and what architectural trade-offs arise when moving cryptographic operations into programmable logic.
A Comprehensive Post-Quantum Cryptography (PQC) Solution based on Physical Unclonable Function (PUF)
This article provides an in-depth analysis of the specific PPA challenges introduced by PQC and elucidates how PUF-PQC leverages its unique dualtrack strategy to deliver a robust and flexible Hardware Root of Trust (HRoT) across diverse application scenarios. Furthermore, it demonstrates the integration of Physical Unclonable Function (PUF) with a NIST SP 800-90B compliant True Random Number Generator (TRNG) to serve as critical components of PUFrt (Root of Trust), ensuring the security of post-quantum key generation starting from the entropy source.
Why Anti-tamper Sensors Matter: Agile Analog and Rambus Deliver Comprehensive Security Solution
If your device processes valuable data, controls a critical function, or connects to a wider network, it’s a target. Attackers don’t just try to break software; they increasingly physically tamper with hardware; probing, fault injecting, or opening enclosures to bypass protections and extract secrets. The consequences range from IP theft and fraud to orchestrated downtime across fleets of connected devices.
Frequently asked questions about Post-Quantum Cryptography IP cores
What is KYBER IP Core?
KYBER IP Core is a Post Quantum IP core from ElectraIC listed on Semi IP Hub.
How should engineers evaluate this Post Quantum?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Post Quantum IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.