Post-Quantum Digital Signature IP Core
The KiviPQC-DSA is an IP core implementing the ML-DSA (Module-Lattice-based Digital Signature Algorithm) a post-quantum cryptogra…
Overview
The KiviPQC-DSA is an IP core implementing the ML-DSA (Module-Lattice-based Digital Signature Algorithm) a post-quantum cryptographic standard defined by NIST FIPS 204. Designed to withstand both classical and quantum computer attacks, ML-DSA ensures the authenticity and integrity of signed data far into the future.
Supporting all ML-DSA parameter sets, the KiviPQC-DSA enables:
- Generate private/public key pair to create signatures and verify signed data
- Generate digital signatures to verify data integrity and detect any unauthorized modifications of signed data
- Ensure authenticity by proving that a digital signature was created by the stated signer (non-repudiation)
The IP core offers dedicated hardware acceleration for the most computationally intensive operations, achieving high throughput and low latency while maintaining a compact logic footprint.
The KiviPQC-DSA IP Core delivers complete protection against time-based side-channel attacks (SCA). Engineered as a self-contained hardware/software co-design, the core integrates all ML-DSA functions and comes ready for seamless deployment. It includes AMBA® hardware interface for straightforward system integration and a generic software API for flexible control from the host processor.
Whether securing firmware updates, authenticating communication, or protecting critical infrastructure, the KiviPQC-DSA offers future-proof signature security for FPGA designs.
| Variant | Description |
| KiviPQC-DSA-Tiny |
Optimized for minimal logic resource usage, thanks to a sequential architecture. Ideal when FPGA resources or power budgets are tight. |
| KiviPQC-DSA-Fast |
Optimized for fast processing. For designs that desire higher performance while maintaining efficient resource utilization. |
Key features
- NIST FIPS 204 compliant
- Supports ML-DSA 44/65/87 parameter sets
- Supports ML-DSA.KeyGen, ML-DSA.Sign, ML-DSA.Verify functions
- Supports pre-hash ML-DSA functions HashML-DSA.Sign and HashML-DSA.Verify
- Supports hedged and deterministic signing
- Supports context string
- Self-contained engine with a minimal attack surface
- Hardware offloading and acceleration for ML-DSA operations
- Protection against timing-based side channel attacks
Easy integration
- Platform agnostic design for any FPGA
- AMBA® AXI4-Lite Interface
- Platform agnostic C-Source Code
- HAL, API and Software drivers included
- Software examples included
- Software User Guide included
- Fast support response within 8 hours
Benefits
- Easy integration: Saves time and effort: Ready to use hardware and software integration.
- Highly cost-efficient: Saves costs: Post-Quantum IP Core with low licensing costs and free evaluation licences.
- Minimal logic utilization: Saves resources: Designed and optimized for area-constrained devices.
Applications
- Software and firmware validation
- Data and message authentication
- Access control & licensing
- Digital content and media
- Configuration or policy validation
- Control command validation
- Critical infrastructures
What’s Included?
- System Verilog RTL Source Code
- Testbenches
- Integration examples
- Software HAL & driver source code
- Software example source code
- Documentation
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
Learn more about Post Quantum IP core
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Frequently asked questions about Post-Quantum Cryptography IP cores
What is Post-Quantum Digital Signature IP Core?
Post-Quantum Digital Signature IP Core is a Post Quantum IP core from KiviCore listed on Semi IP Hub.
How should engineers evaluate this Post Quantum?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Post Quantum IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.