INTC IIP
Interrupt Controller interface provides full support for programmable edge triggered (rising, falling) or sensitive, compatible w…
Overview
Interrupt Controller interface provides full support for programmable edge triggered (rising, falling) or sensitive, compatible with Interrupt Controller Specification. Through its INTC compatibility, it provides a simple interface to a wide range of low-cost devices. INTC IIP is proven in FPGA environment. The host interface of the INTC can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
INTC IIP is supported natively in Verilog and VHDL
Key features
- Compliant with Interrupt controller specification
- Programmable edge triggered (rising, falling) or sensitive (high, low) trigger source
- Configurable number of interrupt sources (up to 31 IRQ,or sensitive (high, low) trigger source one fast IRQ)
- Selectable source for fast IRQ
- Supports up to 31 pending interrupt while servicing a single interrupt
- Eight levels of hardware priority
- Selectable hardware or software interrupt source
- All interrupt sources are maskable
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
Block Diagram
Benefits
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
What’s Included?
- The INTC interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
Learn more about Interrupt Controller IP core
Easy migration from Arm to RISC-V: an L110 case study
Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
A formal-based approach for efficient RISC-V processor verification
A closer look at Arm A-profile support for non-maskable interrupts
SOC Stability in a Small Package
Frequently asked questions about interrupt controller IP cores
What is INTC IIP?
INTC IIP is a Interrupt Controller IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this Interrupt Controller?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Interrupt Controller IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.