Vendor: Aragio Solutions Category: GPIO

I2C I/O Pad Set

The I2C libraries provide the bidirectional I/O for two-line serial communication per Rev.

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TSMC 16nm Pre-Silicon View all specifications

Overview

The I2C libraries provide the bidirectional I/O for two-line serial communication per Rev. 4 of the I2Cbus industry specification. The design is compatible with Standard-mode, Fast-mode, and Highspeed mode I 2C operating modes.

Key features

  • I2C Bi-directional Driver Features
    • Supported I2C operating modes:
      • Standard-mode (Sm) – 100 Kbps data rate
      • Fast mode (Fm) – 400 Kbps data rate
      • Fast mode (Fm+) – 1.0 Mbps data rate
      • High-speed mode (Hs) - 3.4 Mbps data rate
    • Open drain operation only
    • Built-in output slew rate control to meet I2C Tof minimum of (20 x VDDP/5.5V) ns
    • Output enable and mode select
    • Receiver enable
    • ESD protection is accomplished with an SCR (no diode to the positive power supply)
    • Standard LVCMOS compatible input with optional Schmitt trigger (hysteresis)
    • Power-on sequencing independent design with Power-On Control
    • DVDD = 1.62V to 1.98V
    • Pad VDDP = 1.62V to 1.98V – independent of DVDD
    • The circuit consumes no DC supply current in the static state
    • Fault-tolerant to 1.98V at PAD (no current flow when DVDD = 0V)
  • An open-drain design, this cell requires an external pull-up resistor to a high voltage power supply. Designed for a 1.8V I2C bus application, VDDP can track DVDD but it is not necessary. The sizing of the external resistor or appropriate pull-up network is application dependent.

What’s Included?

  • Physical abstract in LEF format (.lef)
  • Timing models in Synopsys Liberty formats (.lib and .db)
  • Calibre compatible LVS netlist in CDL format (.cdl)
  • GDSII stream (.gds)
  • Behavioral Verilog (.v)
  • Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • Databook (.pdf)
  • Library User Guide - ESD Guidelines (.pdf)

Silicon Options

Foundry Node Process Maturity
TSMC 16nm 16nm 160 nm Pre-Silicon

Specifications

Identity

Part Number
RGO_TSMC05_15V18_N5_45F_I2C
Vendor
Aragio Solutions
Type
Silicon IP

Provider

Aragio Solutions
HQ: USA
Aragio is a limited liability corporation (LLC) with headquarters in Plano, Texas. The Company is a full-service provider of semiconductor intellectual property (IP) for integrated circuit (IC) design. Aragio focuses on design solutions for input/output (I/O) system interface cells used for package interconnect. Full I/O library solutions, with robust electrostatic discharge (ESD) protection, are provided for complex integrated circuit padring designs. Aragio serves a very niche market for I/O libraries within the semiconductor industry. The company provides uniform I/O pad sets for a wide range of applications, semiconductor foundries and technologies. It is significant that all IP is owned by Aragio Solutions and nearly all IP developed since the company was formed in 2003 is still in demand and will continue to be in demand for the next decade. As a recognized world leader, Aragio provides its services to numerous clients across Southeast Asia, China, Japan, Europe, and North America.
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Frequently asked questions about GPIO Pad Library IP cores

What is I2C I/O Pad Set?

I2C I/O Pad Set is a GPIO IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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