Vendor: VYUSYNC Design Solutions Category: Video Processing

HEVC/H.265 Decoder - Supports 1080p60, 4:2:2, 12Bits

VYUsync’s HEVC 1080p60, 4:2:2, 12-bit Decoder Core is a optimized video decompression engine targeted primarily at Xilinx FPGAs.

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Overview

VYUsync’s HEVC 1080p60, 4:2:2, 12-bit Decoder Core is a highly optimized video decompression engine targeted primarily at Xilinx FPGAs. It is a universal decoder and has been tested with more than 3000 industry standard test streams. The Decoder is compatible with any ASIC/FPGA/Software encoders in the market. The decoder has been proven on field and the customers are shipping the products with VYUsync HEVC Decoder IP.

It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics. The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures. The decoder solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirements of end users.

Key features

  • Standard: HEVC/H.265 ( ISO/ IEC 23008-2 and ITU-T H.265 )
  • Profiles: Main, Main10, Main 12, Main 10 4:2:2 and Main 12 4:2:2
  • Video Resolutions: Up to 1920 x 1080
  • Frame Rate: 60 fps
  • Bit rate: 75 Mbps. Scalable to 150 Mbps
  • Chroma Format: Monochrome, 4:2:0 & 4:2:2
  • Precision: Bit depths from 8 to 12
  • Input Format: Elementary or Transport stream
  • Output Format: Decoded pictures in frame buffer. Optional serial
  • output with embedded sync information
  • Latency: As low as a few microseconds
  • FPGA: Xilinx Ultrascale and 7-Series FPGAs
  • Arria-10 support coming soon
  • FPGA Resources Numbers for 1920 x 1080p60, 422, 10-bit, 75 Mbps decoder
  • FPGA: Kintex Ultrascale
  • LUTs: 55,000
  • BRAMs: 209
  • DSPs: 185
  • This Does not include memory controller, display controller and TS demultiplexer

Block Diagram

VS-HEVC-DBD125X075AB-XK7 block diagram

Benefits

  • Fully standards compliant - tested with ITU-T & other industry standard test suites.
  • Robust error handling & resilience
  • Processes metadata related to closed captions, AFD, timing & HDR
  • Seamless switching between streams encoded with different settings including different resolutions, chroma formats and bit depths.
  • Extensive options to customize the source code via use of parameters
  • Single chip solution with no processor requirement
  • Optimized resource utilization
  • Easy to integrate and hence faster time-to-market

Applications

  • Broadcast
  • Video Contribution & Distribution decoders
  • Multi-format digital receivers (IRDs)
  • Professional Video
  • High End Consumer Electronics
  • Aerospace & defense
  • Medical
  • Automotive

What’s Included?

  • Source Code or Netlist
  • Simulation Model
  • Hardware Test Platform
  • Build Scripts
  • Test Reports
  • User Manual
  • Design Documentation
  • Constraint Files
  • Test Benches
  • Support for one year

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
VS-HEVC-DBD125X075AB-XK7
Vendor
VYUSYNC Design Solutions
Type
Silicon IP

Provider

VYUSYNC Design Solutions
HQ: India
VYUsync offers a wide range of FPGA based video codecs across multiple video standards HEVC/H.265, H.264/AVC, MPEG-2 and XAVC at a resolution up to 4Kp60 and are highly optimized for deployment across broadcasting, entertainment, medical, space and security industries. VYUsync’s customized and state of the art hardware platforms are major drivers for OEMs to reach their customer’s expectations. VYUsync is recognized as a preferred IP partner by leaders in the broadcast industry for its highly optimized IP cores delivering unparalleled performance
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Learn more about Video Processing IP core

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Frequently asked questions about Video Processing IP

What is HEVC/H.265 Decoder - Supports 1080p60, 4:2:2, 12Bits?

HEVC/H.265 Decoder - Supports 1080p60, 4:2:2, 12Bits is a Video Processing IP core from VYUSYNC Design Solutions listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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