Vendor: Allegro DVT Category: Video Processing

Video Decoder IP optimized for HD use cases

D100 Series is the ultimate multi-format, multi-stream real-time hardware decoder IP core, for all semiconductor manufacturers lo…

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Overview

D100 Series is the ultimate multi-format, multi-stream real-time hardware decoder IP core, for all semiconductor manufacturers looking to integrate a high-performance video decoding solutions into their chips. Built upon a true multi- format architecture, the D100 Series Decoder IP core provides highly flexible solution up to HD/5Mpixels resolution and selectable video codecs. D100 Series supports H.264, HEVC, VP9, AV1 and JPEG formats.

The D100 Series Decoder IP core also generalizes the ultra-low latency decoding down to sub-frame latency and features 8-, 10-bit support and chroma sampling of 4:2:0, 4:4:4.

Supported formats

  • H.265 Main, Main 10 and 4:2:2, 4:4:4 profiles
  • H.264 Baseline, Main, High, 4:2:2, 4:4:4 profiles
  • 8-bit, 10-bit, 12-bit color depth
  • JPEG Baseline
  • AV1 Main, High and Professional Profile
  • VP9 Profile-0, Profile-2

Interfaces

  • AMBA APB interface for control registers
  • AMBA AXI interfaces for data access

What’s Included?

  • RTL source code
  • C control software
  • Bit accurate executable software reference model
  • Documentation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
D100 Series
Vendor
Allegro DVT
Type
Silicon IP

Provider

Allegro DVT
HQ: France
Allegro DVT, headquartered in Grenoble, France, is a world leading company offering digital video processing solutions including compliance streams and video codec semiconductor IPs focused on the H.264, HEVC, AVS2/3, VP9, AV1, VVC and LCEVC standards. Founded in 2003, Allegro is today a recognized market leader in video compression technologies and has been chosen by more than 100 major IC providers, OEMs and broadcasters.
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Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is Video Decoder IP optimized for HD use cases?

Video Decoder IP optimized for HD use cases is a Video Processing IP core from Allegro DVT listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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