Vendor: Allegro DVT Category: Video Processing

LCEVC Video Decoding IP Core

D301 is the MPEG-5 Low Complexity Enhancement Video Coding (LCEVC) decoder IP solution.

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Overview

D301 is the MPEG-5 Low Complexity Enhancement Video Coding (LCEVC) decoder IP solution. The D301 LCEVC decoder IP is optimized for power and silicon area, making it suitable for system-on-chip (SoC) designers to easily integrate LCEVC decoding. It support up to 8Kp60/120 resolution as well as up to 12 bit pixels and 4:4:4 chroma format. LCEVC is an innovative video standard that enhances all existing video codecs including H264, HEVC, VVC and AV1 without the need to replace them. LCEVC delivers better video quality up tu 40% lower bitrate and enables HDR video coding.

Supported formats

  • 8-bit, 10-bit, 12-bit color depth
  • 4:2:0 4:2:2 4:4:4 chroma format
  • Bit accurate executable software reference

Interfaces

  • AMBA APB interface for control registers programming
  • AMBA AXI interfaces for data access

What’s Included?

  • RTL source code
  • C control software
  • Bit accurate executable software reference model
  • Documentation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
D301
Vendor
Allegro DVT
Type
Silicon IP

Provider

Allegro DVT
HQ: France
Allegro DVT, headquartered in Grenoble, France, is a world leading company offering digital video processing solutions including compliance streams and video codec semiconductor IPs focused on the H.264, HEVC, AVS2/3, VP9, AV1, VVC and LCEVC standards. Founded in 2003, Allegro is today a recognized market leader in video compression technologies and has been chosen by more than 100 major IC providers, OEMs and broadcasters.
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Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is LCEVC Video Decoding IP Core?

LCEVC Video Decoding IP Core is a Video Processing IP core from Allegro DVT listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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