Overview
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement and verify designs for various HDMI-based
applications. The silicon-proven HDMI 2.1 IP provides quality digital video and audio transmission with up to 48Gbps aggregate bandwidth for uncompressed 8K resolution at 60Hz refresh rate. It supports the required features of HDMI
2.1 including dynamic HDR and enhanced audio return channel (eARC) and more, ensuring higher video quality and most advanced audio formats. The IP also supports latest HDMI 2.1a addition for Source based tone mapping.
The complete power- and area-optimized HDMI 2.1 RX IP solution encompasses a suite of configurable digital controllers, high-speed, mixed-signal PHYs, PLL, verification IP, High-bandwidth Digital Content Protection (HDCP) embedded security modules (ESMs), Display Stream
Compression (DSC) IP, all pre-integrated and shipped with a reference system. Having all necessary design blocks for the HDMI subsystem enables system- on-chip (SoC) designers to lower integration risk and accelerate time-to-market.
Learn more about PLL IP core
How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.
Jian Yang, Sween Kang (Synopsys)
This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.
This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.
