Vendor: Actt Category: PLL

400MHz Integer-N Low power PLL

This is an analog Integer-N PLL frequency synthesizer, which can generate independent clock with frequency range from 6.25MHz to …

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Overview

This is an analog Integer-N PLL frequency synthesizer, which can
generate independent clock with frequency range from 6.25MHz to 800MHz.It supports 4MHz to 80MHz input
clock frequency range.

Key features

  • Analog PLL frequency synthesizer, output clock range from 200MHz to 800MHz
  • Supports integer-N divider application
  • Duplex output clock signals, high frequency clock and low frequency clock
  • Supports 4MHz to 80MHz input clock frequency range
  • Locked time is less than 250us
  • Low jitter design: <25ps@400MHz (periodic jitter)
  • Operating junction temperature: -40°C ~ +25°C ~ +125°C

Applications

  • MCU
  • IoT SoC

Specifications

Identity

Part Number
400MHz Integer-N Low power PLL
Vendor
Actt
Type
Silicon IP

Provider

Actt
HQ: China
Chengdu Analog Circuit Technology Inc. (Actt) Founded in 2011 is a national high-tech enterprise which is specializing in the designing, licensing, the IPs (intellectual property) of the IC (integrated circuit) products, and can provide one-stop service with its clients. Actt has been involved in low power technology field for more than 10 years. As a result, the products structure including ultra-low power analog IP, high reliability and high performance radio frequency IP and high-speed interface IP of Actt has been gradually established. Actt is holding exceeds 200 patents in worldwide, has developed more than 500 IPs, and successively established partnerships with more than 20 fabs on a global scale. It serves hundreds of IC design enterprises worldwide, its products are widely used in 5G, IoT, smart home, automotive electronics, smart power, wearables, medical electronics, industrial control and other fields. Actt always takes it as its responsibility to provide partners with world-leading products and services, adheres to technology innovation as its core value, committing to becoming a trustworthy and innovative world-class IP provider.
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Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is 400MHz Integer-N Low power PLL?

400MHz Integer-N Low power PLL is a PLL IP core from Actt listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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