Vendor: SmartDV Technologies Category: GDDR

GDDR6 Synthesizable Transactor

GDDR6 Synthesizable Transactor provides a smart way to verify the GDDR6 component of a SOC or a ASIC in Emulator or FPGA platform.

Contact Provider Request Datasheet
Controller View all specifications

Overview

GDDR6 Synthesizable Transactor provides a smart way to verify the GDDR6 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's GDDR6 Synthesizable Transactor is fully compliant with standard GDDR6 Specification and provides the following features.

Key features

  • Supports 100% of GDDR6 protocol standard JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12
  • Supports all the GDDR6 commands as per the specs
  • Supports 2 separate independent channels with point-to-point interface for data, address and command
  • Supports double data rate (DDR) or quad data rate (QDR) data
  • Supports pseudo channel mode operation
  • Supports up to 32GB device density
  • Supports X8 and X16 mode
  • Supports RDQS mode
  • Supports DQ preamble
  • Supports bank group features
  • Supports programmable read/write latency
  • Supports bank grouping and 16 internal banks per channel
  • Supports data bus inversion (DBI) & command address bus inversion (CABI)
  • Supports read/write data transmission integrity secured by cyclic redundancy check
  • Supports input/output PLL/DLL on/off mode
  • Supports read/write EDC on/off mode
  • Supports write data mask function (single/double byte mask)
  • Supports programmable EDC hold pattern for CDR
  • Supports programmable CRC READ/WRITE latency
  • Supports low power modes
  • Supports Refresh Management(RFM)
  • Supports auto refresh & self-refresh modes
  • Supports on-die termination operation
  • Supports vendor ID1 and ID2 for identification
  • Supports command address, WCK2CK,read/write training mode’s
  • Supports IEEE.1149.1 boundary scan operation
  • Supports programmable clock frequency of operation
  • Checks for following:
    • Check-points include power on, initialization and power off rules
    • State based rules, active command rules
    • Read/write command rules etc
    • All timing violations
  • Supports all mode registers programming
  • Supports power down features
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

Block Diagram

GDDR6 Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the GDDR6 testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
GDDR6 Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about GDDR IP core

Selection Criteria for Using DDR, GDDR or MobileDDR Memories in System Designs

This paper will include a short review of the key features of DDR, GDDR and MobileDDR memory architectures, covering power, speed and cost characteristics as well as key functionality differences that can impact overall system architecture. Using real system design experiences each of the main memory architectures will be used to address system design challenges of sustained bandwidth, reliability, access priority, power savings, and interface requirements.

SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference

Large Language Models (LLMs) have gained popularity in recent years, driving up the demand for inference. LLM inference is composed of two phases with distinct characteristics: a compute-bound prefill phase followed by a memory-bound decode phase. This paper proposes SPAD (Specialized Prefill and Decode hardware), adopting a less-is-more methodology to design specialized chips tailored to the distinct characteristics of prefill and decode phases.

High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4

HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become analogous to the Artificial Intelligence (AI) boom that is everywhere in today’s world. HBM is also increasingly being used in other applications like Data centers, autonomous driving systems, servers, cloud computing just to mention few domains where bandwidth and performance in a key requirement.

Designing the AI Factories: Unlocking Innovation with Intelligent IP

The rapid evolution of artificial intelligence (AI) is reshaping the technological landscape, driving unprecedented demands on computing infrastructure. At the heart of this transformation lie innovations in intellectual property (IP) that enable scalable, efficient, and performance-driven AI factories.

Frequently asked questions about GDDR Interface IP

What is GDDR6 Synthesizable Transactor?

GDDR6 Synthesizable Transactor is a GDDR IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this GDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP