Vendor: Cadence Design Systems, Inc. Category: GDDR

Simulation VIP for GDDR6

Sign-off model for dozens of production designs.This Cadence® Verification IP (VIP) provides support for the JEDEC® Graphics Doub…

Overview

Sign-off model for dozens of production designs.

This Cadence® Verification IP (VIP) provides support for the JEDEC® Graphics Double Data Rate (GDDR6) SGRAM GDDR6 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for GDDR6 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

The GDDR6 standard is is a modern type of synchronous graphics random-access memory (SGRAM) with a high bandwidth ("double date rate") interface designed for use in graphics cards, game consoles, and high-performance computation.

Supported specification: JEDEC JESD250, JESD250A, JESD250B, and JESD205C specification.

Key features

  • Speed
    • Supports up to 16Gbps with current vendor datasheets
  • Device Density
    • Supports a wide range of device densities from 8Gb to 32Gb
  • Device Configuration
    • Supports x16/x8 mode configuration; Supports Pseudo-channel (PC) mode configuration
  • Bank Architecture
    • 16B and BankGroup supported
  • Clock
    • CK (DDR), WCK (DDR, QDR), DFS (Clock frequency change)
  • Supported Commands
    • Write: WOM, WOMA, WDM, WDMA, WSM, WSMA, WRTR
    • Read: RD, RDA, RDTR
    • Precharge: PREab, PREpb
    • Power down: PDE, PDX
    • Self refresh: SRE, SRX
    • Refresh: REFab, REFpb, REFp2b
    • NOP, MRS, Activate, CAT
  • Initialization
    • Power-up sequence, Stable Power Sequence
  • Interface Trainings
    • Command address training, WCK2CK training, Read training, Write training
  • Command Address Bus Inversion
    • The number of CA lines driving a LOW level can be limited to 5 in 2-channel mode or 7 in PC mode for 8Gb, 12Gb and 16Gb densities and limited to 6 in 2-channel mode or 8 in PC mode for 24Gb and 32Gb densities
  • Data Bus Inversion
    • Data on the bus can be inverted during both read and write to save power. Data Bus Inversion the feature can be set through mode register
  • Error Detection Code
    • Supports Error Detection Code hold pattern, CRC, and special EDC in other states
  • Tccd Reads and Writes
    • Supports all combinations of Reads and Writes placed Tccd apart
  • Self Refresh
    • Supports Hibernate Self Refresh with VDDQ off

Block Diagram

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Simulation VIP for GDDR6
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.

Learn more about GDDR IP core

Selection Criteria for Using DDR, GDDR or MobileDDR Memories in System Designs

This paper will include a short review of the key features of DDR, GDDR and MobileDDR memory architectures, covering power, speed and cost characteristics as well as key functionality differences that can impact overall system architecture. Using real system design experiences each of the main memory architectures will be used to address system design challenges of sustained bandwidth, reliability, access priority, power savings, and interface requirements.

SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference

Large Language Models (LLMs) have gained popularity in recent years, driving up the demand for inference. LLM inference is composed of two phases with distinct characteristics: a compute-bound prefill phase followed by a memory-bound decode phase. This paper proposes SPAD (Specialized Prefill and Decode hardware), adopting a less-is-more methodology to design specialized chips tailored to the distinct characteristics of prefill and decode phases.

High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4

HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become analogous to the Artificial Intelligence (AI) boom that is everywhere in today’s world. HBM is also increasingly being used in other applications like Data centers, autonomous driving systems, servers, cloud computing just to mention few domains where bandwidth and performance in a key requirement.

Designing the AI Factories: Unlocking Innovation with Intelligent IP

The rapid evolution of artificial intelligence (AI) is reshaping the technological landscape, driving unprecedented demands on computing infrastructure. At the heart of this transformation lie innovations in intellectual property (IP) that enable scalable, efficient, and performance-driven AI factories.

Frequently asked questions about GDDR IP

What is Simulation VIP for GDDR6?

Simulation VIP for GDDR6 is a GDDR IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this GDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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