3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process
3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process
- Fujitsu
- 40nm
- LP
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and high-speed interfaces such as SerDes.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process
3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process
3.3V to 1.1V / 600mA PWM, Switching Regulator using MIFS C40LP Logic Process
3.3V to 1.1V / 600mA PWM, Switching Regulator using MIFS C40LP Logic Process
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process