Processor Architecture for High Performance Video Decode
Processor Architecture for High Performance Video Decode
Vendor:
EnSilica
Category:
Filters Transforms
Digital FIR filter with APB interface
The eSi-FIR core provides an interface to filter and decimate time interleaved multi-channel data.
Overview
The eSi-FIR core provides an interface to filter and decimate time interleaved multi-channel data.
Key features
- Programmable decimation filter rate between 1 and 4.
- Programmable number of taps between 3 and 64.
- Programmable 16-bit coefficients.
- 16-bit data
- A new filter output is available every “TAPS” clock cycles.
- Scaling and rounding of filter output to 22 bits.
- No requirement for symmetric or anti-symmetric filters
- AMBA APB control register interface
- DMA data interface
Benefits
- Very low resource requirements
- Within +/-1 LSB of floating point reference model
What’s Included?
- RTL source code
- Testbench with various stimulus generation
- Synthesis scripts
- MATLAB model
Specifications
Identity
Part Number
eSi-FIR
Vendor
EnSilica
Type
Silicon IP
Provider
EnSilica
HQ:
UK
EnSilica is a leading fabless design house focused on custom ASIC design and supply for OEMs and system houses, and IC design services for companies with their own design teams. The company has world-class expertise in supplying custom analog, mixed signal and digital IC’s to its international customers in the automotive, industrial, healthcare and consumer markets.
The company also offers a broad portfolio of core IP covering cryptography, Radar and communications systems. EnSilica has a track record in delivering high quality solutions to demanding industry standards.
Learn more about Filters Transforms IP core
No size fits all for signal processing on FPGA (RF Engines)
No size fits all for signal processing on FPGA (RF Engines)
Employing general-purpose processors for radio DSP
Employing general-purpose processors for radio DSP
Do's and Don'ts of Architecting the Right FPGA Solution for DSP Design
Finally a Practical ''Do and Don't'' primer on architecting FPGA solutions for DSP design. With more do's than don’ts, the article is a down-to-basics look at how to avoid the pitfalls and realize device benefits
10 FPGA Design Techniques You Should Know
Regardless of whether you are using VHDL, System Verilog, or a different design capture language, there are a number of universal design techniques with which FPGA engineers should be familiar, from the very simple to the most advanced.
How to implement double-precision floating-point on FPGAs
The real results of a double-precision matrix multiply core that can easily be extended to a full DGEMM benchmark are demonstrated.
Frequently asked questions about Filters and Transforms IP cores
What is Digital FIR filter with APB interface?
Digital FIR filter with APB interface is a Filters Transforms IP core from EnSilica listed on Semi IP Hub.
How should engineers evaluate this Filters Transforms?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Filters Transforms IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.