Vendor: Certus Semiconductor Category: Analog

Analog I/O Library with a custom 12V ESD Solution IN GF 55nm

An Analog I/O Library in GlobalFoundries 55nm LPx-BCDlite technology This I/O library is a silicon-proven, flip-chip-optimized an…

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GlobalFoundries 55nm Silicon Proven View all specifications

Overview

An Analog I/O Library in GlobalFoundries 55nm LPx-BCDlite technology

This I/O library is a silicon-proven, flip-chip-optimized analog and mixed-signal I/O Library for GlobalFoundries 55nm BCD technology. It provides a comprehensive set of 1.8V, 3.3V, 5V, and 12V analog I/O and power pads, designed for robust ESD protection, flexible pad-ring construction, and reliable operation across industrial temperature ranges. The library is well suited for PMICs, mixed-signal ASICs, sensor interfaces, and companion SoCs requiring multiple voltage domains and high-reliability ESD.

Technology & Process

Parameter Specs
Foundry GlobalFoundries
Node 55nm BCD
BEOL 1P5M
Package Flip-Chip
Min. Bump Pitch 60um
Max Bump Height 75um

Operating Conditions

Parameter Value
Analog Supply Voltages 1.8V, 3.3V, up to 12V
Temp Range -40C to 125C
ESD Rating 2kV HBM, 500V CDM
Latch-up >150mA

Library Architecture

  • CommonAnalog Bus Architecture
  • Voltage domains must not be mixed within the same pad ring
  • High-voltage pads can be integrated into low-voltage pad rings while maintaining isolation
  • Defined rules for pad spacing, power-ground pairing, ESD distance

High-Voltage Support

  • 12V nominal operation
  • Triple-wide HV cells (150um) with multiple top-metal anchors
  • HV analog and HV power pads are self-contained for ESD
  • HVsignals can coexist with 1.8V and 3.3V pad rings

Key features

  • Multi-voltage analog I/O support
  • Flip-chip-optimized architecture
  • Self-protecting high-voltage cells
  • Isolated power domains
  • Robust ESD performance: Qualified to 2kV HBM and 500V CDM
  • Latch-up immue design with >150mA latch-up robustness
  • Wide temp. operation
  • Nospecial process options required

Benefits

  • Reduces need for custom pad development
  • Enables rapid pad-ring assembly
  • Simplifies multi-voltage mixed-signal designs
  • Support high-reliability and industrial applications
  • Proven compatiblity with flip-chip applications

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 55nm 55 550 nm Silicon Proven

Specifications

Identity

Part Number
MS55
Vendor
Certus Semiconductor
Type
Silicon IP

Provider

Certus Semiconductor
HQ: United States
Certus Semiconductor has assembled several of the world’s foremost experts in IO and ESD design to offer our clients the ability to affordably tailor their IO libraries into the optimal fit for their products. Certus is offering the semiconductor industry a unique approach to custom IO libraries, including tailored IO designs, and ESD solutions based on simulations leveraging specialized silicon ESD models. In addition to offering fast turnaround custom IO designs, Certus offers independent ESD design, review and debug services. Through partnerships, Certus is also able to provide ESD testing & TLP support.
Contact Certus Semiconductor

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Frequently asked questions about Analog I/O Pad Library IP cores

What is Analog I/O Library with a custom 12V ESD Solution IN GF 55nm?

Analog I/O Library with a custom 12V ESD Solution IN GF 55nm is a Analog IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.

How should engineers evaluate this Analog?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Analog IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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