The I3C library provides a bi-directional I/O driver designed for the I3C two-line interface. It is compliant with the MIPI Specification for I3C –Version 1.1, 27 Novenber 2019.
The design supports the IC3 push-pull and open-drain modes as well as legacy Fm and Fm+ open-drain modes at the bus operating voltages of 1.2V and 1.8V.
This 5nm library is available in an inline flip chip implementation.
To design a functional I/O power domain with this cell, an additional library is required – 1.8V Support: Power. That library contains isolated analog I/O, and a full complement of power cells along with spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while
I3C I/O Library
Overview
Key Features
- Supported I3C operating modes:
- I3C push-pull mode – up to 12.5 MHz
- I3C open-drain mode – up to 12.5 Mbps data rate
- Legacy Fast mode (Fm) – up to 400 Kbps data rate
- Legacy Fast mode (Fm+) – up to 1.0 Mbps data rate
- Output enable and mode select
- Receiver enable
- Standard LVCMOS compatible input with optional Schmitt trigger (hysteresis)
- ESD protection is accomplished with stacked NMOS breakdown devices
- Power-on sequencing independent design with Power-On Control
- DVDD = 1.2V or 1.8V
- Pad VDDP (open-drain) = 1.65V to 1.95V or 1.20V to 1.30V – independent of DVDD
- The circuit consumes no DC supply current in the static state in the open-drain modes
- Fault-tolerant to 1.98V at PAD (no current flow when DVDD = 0V)
- In open-drain modes, this cell requires a pull-up to a high voltage power supply (VDDP). The sizing of an external resistor or appropriate pull-up network is application dependent.
Deliverables
- Physical abstract in LEF format (.lef)
- Timing models in Synopsys Liberty formats (.lib and .db)
- Calibre compatible LVS netlist in CDL format (.cdl)
- GDSII stream (.gds)
- Behavioral Verilog (.v)
- Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- Databook (.pdf)
- Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
TSNC, N5
Maturity
Pre-Silicon
Availability
Available Now
TSMC
Pre-Silicon:
5nm
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