Overview
The AL-H264E-4KI422-HW is a hardware-based, feature rich, low latency, high video quality H.264 (AVC) UHD Hi422 Intra encoder IP core. The AL-H264E-4KI422-HW encoder pairs up with the Atria Logic AL-H264D-4KI422-HW low latency decoder for low latency end-to-end links.
The encoder is targeted for medical imaging, broadcast, enterprise/CE and industrial applications. Medical imaging applications include endoscopy, micro surgery and remote assisted surgery and diagnostics. Broadcast applications include video recorders for news and event coverage, film sets and production studios, as well as real-time monitoring of video shoots. Enterprise/CE applications include HDBaseT video transmission over CAT5/6 Ethernet cabling to computer monitors and UHD TV displays. Industrial applications include monitoring of manufacturing plants, and remote manipulation of mobile or fixed light or heavy machinery.
The encoder supports the H.264 Hi422 (High-422) profile at Level 5.1 (3840x2160p30) for Intra-only coding. Support for 10-bit video content means that there is no degradation of grayscale or color gradients in terms of banding. Support for YUV 4:2:2 video content means that there is better color separation, especially noticeable for red colors, which provides much sharper image details. These video quality aspects are especially important in case of medical imaging applications.
Support for Intra-only encoding allows the encoder to encode uncompressed video at frame latencies. A macroblock-line level pipelined architecture brings the latency further down to sub-frame level, at about 0.3msec. When connected to the Atria Logic AL-H264D-4KI422-HW low latency decoder via an IP network, the glass-to-glass latency is about 0.6msec, not taking into account any transmission latency, and otherwise 2 frames with transmission in case of an IP network. Such low latency is important for any closed-loop man-machine application as mentioned here above.
The encoder is implemented in a single Xilinx Zynq-7000 XC7Z045 all programmable SoC. The efficient implementation only takes up 63% of the programmable logic and DSP resources and 36% of the available RAM, leaving ample room for implementation of any other required circuitry. Integration of a Gb Ethernet MAC provides streaming over IP support.
Provider
Atria Logic, Inc.
HQ:
USA
Atria Logic is a leading provider of HW/SW FPGA and SoC IP cores and design engineering services, specializing in applications for medical imaging, multimedia, storage and networking. In addition, we also specialize in heterogeneous computing engineering services for computer vision applications in such applications as industrial automation, video surveillance and automotive.
Our IP core portfolio includes H.264 video encoders and decoders, H.264 players, DDR I/II/III and QDR IV Extreme Performance PHY and memory controllers, USB 2/3 controllers, PCIe Gen 1/2 PHYs, NVMe validation test suites, and Gb Ethernet MAC controllers. Our IP cores have been designed for ease of reuse and configurability to speed up SoC and FPGA implementations.
Our design services include IP customization, SoC integration, FPGA and SoC implementations, firmware development, software porting and optimization.
We are headquartered in Sunnyvale, California, USA, in the heart of Silicon Valley.
Technology Focus:
Video/Image processing
Heterogeneous Processing
High Power Computing
Computer Vision and Video Analytics
High speed memory controllers and Standard bus architectures
Network Processing
FPGA/ASIC/SoC design services
HW/SW domain consultancy and services
Business Domains
Medical Imaging
Video Surveillance
Industrial Automation
Enterprise and Datacenter Storage
Broadcast
Automotive Assisted Driver Assistance Systems
Learn more about Video Processing IP core
This paper describes an FPGA-based high-definition video processing platform. The platform supports a wide range of applications including flat-panel TV, projection TV and video monitor.
Configurable Processors for Video Processing SOCs
Programmable FPGA devices are the perfect choice for interfacing with multiple high-resolution image sensors simultaneously...
A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing
Building a high-performance, quad-channel H.264 encoder using low-cost, low-power FPGA architecture.
Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.
