Vendor: Secure-IC Category: Root Of Trust

Secure Debug Hardware IP

The Secure Debug IP provides isolation between 2 domains.

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Overview

The Secure Debug IP provides isolation between 2 domains. It will ensure isolation between the HOST System on one hand, and the HSM System on another hand. Both(HOST an dHSM)can access the IP through an AXI Slave interface.

Secure-IC’s Secure Debug IP is a hardware IP that provides:

  • Hardware Authentication scheme between the HOST and the HSM.
  • Communication interface between the HOST and the HSM,mainly for the purpose of the maintenance of the System-on-Chip.

This IP is controlled by a HOST through an AXI Slave Interface. The purpose of the Secure Debug IP is to provide the following services:

  • Get life-cycle information from the HSM.
  • Provide a Hardware Authentication scheme.
  • Allow only one HOST to be logged in at the same time.
  • Allow to open the HSM debug por tonly if life cycle mode values allow it.
  • Receive Maintenance requests (first programming, update, lifecycle ...) from an external user.

Block Diagram

SCZ_IP_SDEBUG block diagram

Applications

  • Automotive
  • IoT
  • eHealth
  • Defense
  • Payments
  • Servers
  • Smart Grid
  • Identity
  • Media & Entertainment
  • Memory & Storage
  • Consumer Electronics
  • Edge & Cloud
  • Trusted Computing
  • AI
  • Printer
  • Industry

What’s Included?

  • RTL code 
  • SW Drivers 
  • Scripts for  implementation 
  • Self-checking RTL test-bench
  • Documentation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
SCZ_IP_SDEBUG
Vendor
Secure-IC
Type
Silicon IP

Provider

Secure-IC
HQ: France
With presence and customers across 5 continents, Secure-IC is the rising leader and the only global provider of end-to-end cybersecurity solutions for embedded systems and connected objects. Driven by a unique approach called PESC (Protect, Evaluate, Service & Certify), Secure-IC positions itself as a partner to support its clients throughout and beyond the IC design process. Relying on innovation and research activities, Secure-IC provides Silicon-proven and cutting-edge protection technologies, integrated Secure Elements and security evaluation platforms to reach compliance with the highest level of certification for different markets (such as automotive, AIoT, defense, payments & transactions, memory & storage, server & cloud). Discover in preview of Secure-IC new Securyzr Server to manage the security of heterogeneous fleets of IoT devices throughout their lifecycle
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Learn more about Root Of Trust IP core

Root of Trust: A Security Essential for Cyber Defense

Imagine a datacenter powering critical cloud services, silently compromised by a tampered chip inserted during manufacturing. In most cases, the malware would be practically impossible to remove and could persist across formats/reinstalls !

Why Hardware Root of Trust Needs Anti-Tampering Design

The hardware root of trust (HRoT) provides the trust base (root key), hardware identifier (UID), hardware unique key (HUK), and entropy required for the secure operation of the entire chip and therefore is often the focus of hacker attacks. If the design can’t effectively resist attacks, hackers can easily obtain the secrets of the entire chip. Attackers can use the secrets to crack identity authentication and data encryption and steal product design know-how, causing application security problems.

Frequently asked questions about Root of Trust IP cores

What is Secure Debug Hardware IP?

Secure Debug Hardware IP is a Root Of Trust IP core from Secure-IC listed on Semi IP Hub.

How should engineers evaluate this Root Of Trust?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Root Of Trust IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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