Vendor: Zyxx Tech Category: Symmetric Crypto

Chacha20-Poly1305 IP for FPGA and ASIC

ChaCha20-Poly1305 is an AEAD algorithm based on the very fast ChaCha20 stream cipher with the Poly1305 MAC.

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Chacha20 View all specifications

Overview

ChaCha20-Poly1305 is an AEAD algorithm based on the very fast ChaCha20 stream cipher with the Poly1305 MAC. It was proposed by It is standardized in the RFC 84391 and is widely used in TLS 1.2, TLS 1.3, SSH, Wiregard…

Key features

  • Available in 2 versions:
  • Fast : High bandwith with low latency and high frequency
  • Small : Higher latency but smaller footprint
  • Full standard support : Zyxx ChaCha20-Poly1305 supports full specification of the ChaCha20-Poly1305 standard
  • AXI4 compatible interface can be added as an option
  • Available for a wide range of FPGA vendors : AMD (Xilinx), Intel (Altera), Microchip, Lattice, Achronix, QuickLogic.
  • Available for Asics

Benefits

  • Lowest footprint on the market

What’s Included?

  • Netlist, sourcecode

Specifications

Identity

Part Number
Zyxx ChaCha20
Vendor
Zyxx Tech
Type
Silicon IP

Security

Crypto Algorithm
Chacha20

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Zyxx Tech
HQ: France
Based in Paris, Zyxx Tech specializes in designing, developing, and optimizing cryptographic Intellectual Properties (IPs) that are tailor-made for FPGA and ASIC implementations.
Contact Zyxx Tech

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Frequently asked questions about Symmetric Cryptography IP cores

What is Chacha20-Poly1305 IP for FPGA and ASIC?

Chacha20-Poly1305 IP for FPGA and ASIC is a Symmetric Crypto IP core from Zyxx Tech listed on Semi IP Hub.

How should engineers evaluate this Symmetric Crypto?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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