C-PHY Verification IP
The C-PHY Verification IP provides an effective & efficient way to verify the components interfacing with C-PHY interface of an I…
Overview
The C-PHY Verification IP provides an effective & efficient way to verify the components interfacing with C-PHY interface of an IP or SoC. The C-PHY VIP is fully compliant with MIPI C-PHY Specification version 2.1 The VIP is light weight with easy plug-and- play interface so that there is no hit on the design cycle time.
Key features
- Compliant to MIPI C-PHY Specification version 2.1 with PPI interface.
- Supports all configuration of a data lane module as specified in Figure 6 of C-PHY specification version 2.1 for Data Lane Module (MFAA & SFAA, MFAE & SFAE, MFEA & SFEA, MFAN & SFAN, MFEE & SFEE, MFEN & SFEN).
- Supports ULPS, Triggers and LPDT in low power escape mode.
- Bi-directional Data lane turnaround is supported for escape mode
- Configurable number of Data Lanes.
- Supports High-Speed mode and Low Power Escape and Control modes.
- Supports continuous and non-continuous clock behaviour.
- Supports 16-bit to 7-symbol Mapper and 7-symbol to 16-bit Demapper.
- Supports symbol encoding and decoding.
- Supports dynamically configurable modes.
- Strong Protocol Monitor with real time exhaustive programmable checks.
- Supports Dynamic as well as Static Error Injection scenarios.
- On the fly protocol checking using assertions.
- Built in Coverage analysis.
- Provides a comprehensive user API (callbacks) in Master and slave.
- Graphical analyser to show transactions for easy debugging.
Block Diagram
Benefits
- Available in native System Verilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and coverage points with connectivity examples for all the components
- Consistency of interface, installation, operation, and documentation across all our VIPs
- Provide complete solutions and easy integration in IP and SoC environment
What’s Included?
- MIPI C-PHY Master/Slave BFM/Agent
- MIPI C-PHY Monitor
- MIPI C-PHY Scoreboard
- Testbench Configurations
- Test Suite (Available in Source code)
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual and Release Notes
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Standards & Interfaces
Provider
- To create world class Verification IP Solutions
- To provide expert consultancy to ASIC & SoC Design companies
- To design SOCs from Architecture to Working Silicon
- To be the leading provider of Semiconductor IP Solutions
- To be a one-stop-shop for Design and Verification
- Customer Success
- Commitment to Quality
- Quality of Products
- Quality of Engineers
- Best in class Customer Support
- Ethics and Integrity
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Frequently asked questions about MIPI PHY IP
What is C-PHY Verification IP?
C-PHY Verification IP is a MIPI PHY IP core from Truechip Solutions listed on Semi IP Hub.
How should engineers evaluate this MIPI PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.