Vendor: MVD Cores Category: Broadcast

ATSC Remultiplexer N-to-M

The MVD ATSC Remultiplexer core analyses the MPEG TS stream inputs and gives access to the followings information and statistics …

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Overview

The MVD ATSC Remultiplexer core analyses the MPEG TS stream inputs and gives access to the followings information and statistics :
• Incoming TS Stream features ( TS_ID, Version, Tables ...)
• Incoming/ Payload/ Outcoming rates
• Program List and bandwidth for each program.
• Program Information (Short Name, Program Number, Access Control Flags (VCT & PID Frame Header), etc...)

Then, it filters user selected programs and regenerates PSIP tables such as such as PAT, CAT, PMTs (according to configuration), MGT, STT, VCT (Cable or Terrestrial) , EIT0->EIT3, RRT.

Not filtered PMT program and others PID which do not correspond to any program or PSIP tables are filtered.

PMTs are re-generated according to the modifications to apply to the output stream.

CAT and related PIDs are filtered according to the configuration of the remultiplexer.

The ATSC Remultiplexer core allows the filtering of programs of ATSC MPEG TS flows compliant with the standards:
• ISO13818-1
• A53/Part 3; A65:2009

Key features

  • Supported FPGA families: Xilinx Spartan-6, Virtex-6, Artix-7, Kintex-7, Virtex-7, Zynq
  • N SPI input / M SPI output (N and M from 1 to 8)
  • Adapt one or several MPTS/SPTS stream rate into one or several MPTS by filtering and multiplexing complete services
  • Management of PSIP tables (automatic tables generator) according to ATSC A/65:2009, A/53:part 3 and ISO 13818-1.
  • Configurable via an RS232 link or I²C link
  • Service filtering
  • Full PCR re-stamping
  • Master/Slave control of input/output mux flows
  • Statistical service bandwidth estimation per input
  • Maximize output payload bandwidth thanks to smoothing FIFO.
  • Common output Smoothing FIFO can be implemented as block RAM, external Synchronous SRAM memory or external DDR3 (same memory than program memory for Spartan-6 only using MCB)
  • Size of the output smoothing FIFO is configurable and common for all output channels.
  • Full synthesizable RTL design (not delivered) for easy customization
  • Netlist version available for ISE and VIVADO
  • CPU Interface to control MVD Modulator Core

Block Diagram

MVD_ATSC_REMUXN-M block diagram

Applications

  • The MVD ATSC Remultiplexer allows to adapt and multiplex transmodulator bandwidth from several sources towards one or several modulators.

What’s Included?

  • Datasheet
  • Netlist for core generation
  • VHDL top file
  • VHDL source code : can be delivered as an option under NDA and other specific clauses

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
MVD_ATSC_REMUXN-M
Vendor
MVD Cores
Type
Silicon IP

Provider

MVD Cores
HQ: France
MVD Cores is an engineering team highly specialized in Digital Video Broadcasting (DVB) and FPGA technologies. We provide IP cores for Processing, Transporting and Transmission of MPEG, DVB, ATSC & IPTV standards for Xilinx FPGAs. The products and services catalog contains a wide range of on-the-shelf IPs to build solutions to carry MPEG-TS to RF. Our IPs cover almost all worldwide standards of current technologies for broadcasting over Digital Terrestrial Television (DTT), Cable TV (CATV) and Satellite.
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Frequently asked questions about broadcast wireless IP cores

What is ATSC Remultiplexer N-to-M?

ATSC Remultiplexer N-to-M is a Broadcast IP core from MVD Cores listed on Semi IP Hub.

How should engineers evaluate this Broadcast?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Broadcast IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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