Learn more about Arithmetic Units IP core
This article provides an in-depth analysis of the specific PPA challenges introduced by PQC and elucidates how PUF-PQC leverages its unique dualtrack strategy to deliver a robust and flexible Hardware Root of Trust (HRoT) across diverse application scenarios. Furthermore, it demonstrates the integration of Physical Unclonable Function (PUF) with a NIST SP 800-90B compliant True Random Number Generator (TRNG) to serve as critical components of PUFrt (Root of Trust), ensuring the security of post-quantum key generation starting from the entropy source.
KiviCore´s blog post discusses Quantum-safe key exchange with NIST FIPS 203 ML-KEM and how IP cores simplify PQC integration on FPGA and SoCs.
In today’s fast-paced silicon industry, hardware design is under constant pressure to innovate, iterate, and ship faster. Traditional Register Transfer Level (RTL) design processes—though foundational—are time-consuming, error-prone, and heavily reliant on manual expertise. With growing design complexity and shrinking time-to-market, the need for automation in digital design is more critical than ever.
Given the prominence of the LTE protocol in wireless devices, it is surprising that there are very few DFT FPGA circuit implementations from which to choose. This is likely due to the complexity of the circuit, which must accommodate run-time choice of many and large non-power-of-two transforms, requiring multiple radices for efficient DFT calculation.
DLX is an open source microprocessor, it’s free and it has never been implemented in a commercial ASIC (Application Specific Integrated Circuit) design. The objective of this project is to use the DLX microprocessor implemented with Wishbone bus interface for a SoC (System-on-Chip) design.
Computing dons new suits as required
