APB UART 16550
This is a implementation of a 16550 UART.
Overview
This is a complete implementation of a 16550 UART. The UART contains the following main sections:
- Configuration Registers
- Baud Rate Generator
- Transmitter
- Receiver
- Interrupt Generation Logic
- Modem Control Logic
Configuration registers are written and read by the processor. The baud rate generator produces timing strobes at the baud rate (for the transmitter) and at 16 times the selected baud rate (for the receiver). The UART clock can be asynchronous to the APB clock. The receiver examines the incoming data and uses the first edge of the start bit to determine the bit timing. The transmit and receive paths can be configured to use a single register for data or to use FIFOs. Finite State Machines (FSMs) control the transmit and receive sections. Various error conditions can cause an interrupt to be generated.
Key features
- AMBA® APB Compatible
- 16450 and 16550 Compatible Modes
- Modem control
- Programmable baud rates
- FIFO and non-FIFO modes
- Transmit and Receive FIFOs with parameterizable depth
- Interrupt control
Block Diagram
What’s Included?
- Verilog Source
- Complete Test Environment
- APB Bus Functional Model
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about UART IP cores
What is APB UART 16550?
APB UART 16550 is a UART IP core from Silvaco, Inc. listed on Semi IP Hub.
How should engineers evaluate this UART?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.